Datasheet

659
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
If SPI_RDR has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as
this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit.
Figure 33-5, shows a block diagram of the SPI when operating in Master mode. Figure 33-6 on page 660 shows a flow
chart describing how transfers are handled.
33.7.3.1 Master Mode Block Diagram
Figure 33-5. Master Mode Block Diagram
Shift Register
SPCK
MOSI
LSBMSB
MISO
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSRx
CPOL
NCPHA
BITS
Peripheral clock
Baud Rate Generator
SPI_CSRx
SCBR
NPCSx
NPCS0
NPCS0
0
1
PS
SPI_MR
PCS
SPI_TDR
PCS
MODF
Current
Peripheral
SPI_RDR
PCS
SPI_CSRx
CSAAT
PCSDEC
MODFDIS
MSTR