Datasheet

657
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
 The pins NPCS0 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only
in Master mode.
33.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These two
parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters
has two possible states, resulting in four possible combinations that are incompatible with one another. Consequently, a
master/slave pair must use the same parameter pair values to communicate. If multiple slaves are connected and require
different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 33-4 shows the four modes and corresponding parameter settings.
Figure 33-3 and Figure 33-4 show examples of data transfers.
Figure 33-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Table 33-4. SPI Bus Protocol Mode
SPI Mode CPOL NCPHA Shift SPCK Edge Capture SPCK Edge SPCK Inactive Level
0 0 1 Falling Rising Low
1 0 0 Rising Falling Low
2 1 1 Rising Falling High
3 1 0 Falling Rising High
6
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined.
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