Datasheet

538
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
29.17.23PMC Peripheral Clock Enable Register 1
Name: PMC_PCER1
Address: 0x400E0500
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
• PIDx: Peripheral Clock x Enable
0: No effect.
1: Enables the corresponding peripheral clock.
Notes: 1. To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
–––––PID34PID33PID32