Datasheet

523
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
29.17.10PMC Clock Generator PLLB Register
Name: CKGR_PLLBR
Address: 0x400E042C
Access: Read/Write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
• DIVB: PLLB Front-End Divider
0: Divider output is stuck at 0 and PLLB is disabled.
1= Divider is bypassed (divide by 1)
2 up to 255 = clock is divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0: The PLLB is deactivated (PLLB also disabled if DIVB = 0).
1 up to 62 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
31 30 29 28 27 26 25 24
––––– MULB
23 22 21 20 19 18 17 16
MULB
15 14 13 12 11 10 9 8
– – PLLBCOUNT
76543210
DIVB