Datasheet

510
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
29.16 Register Write Protection
To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be write-
protected by setting the WPEN bit in the “PMC Write Protection Mode Register” (PMC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the “PMC Write Protection Status Register”
(PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the PMC_WPSR.
The following registers can be write-protected:
 “PMC System Clock Enable Register”
 “PMC System Clock Disable Register”
 “PMC Peripheral Clock Enable Register 0”
 “PMC Peripheral Clock Disable Register 0”
 “PMC Clock Generator Main Oscillator Register”
 “PMC Clock Generator PLLA Register”
 “PMC Clock Generator PLLB Register”
 “PMC Master Clock Register”
 “PMC USB Clock Register”
 “PMC Programmable Clock Register”
 “PMC Fast Start-up Mode Register”
 “PMC Fast Start-up Polarity Register”
 “PMC Peripheral Clock Enable Register 1”
 “PMC Peripheral Clock Disable Register 1”
 “PMC Oscillator Calibration Register”