Datasheet

498
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor.
The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master Clock Register
(PMC_MCKR).
It is forbidden to change the 4/8/12 MHz fast RC oscillator, or the main selection in CKGR_MOR register while the master
clock source is the PLL and the PLL reference clock is the fast RC oscillator.
The user must:
 Switch on the main RC oscillator by writing 1 in CSS field of PMC_MCKR.
 Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
 Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR.
 Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
 Wait for LOCK flag in PMC_SR.
 Switch back to PLL by writing the appropriate value to CSS field of PMC_MCKR.