Datasheet

419
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
25.3 Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several
memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Thus it is
possible to boot at the same address while using different AHB slaves.
25.4 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some
masters. This technique reduces latency at the first access of a burst or single transfer. Bus granting sets a default
master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated default
master. A slave can be associated with one of the three implementations of default masters:
No default master
Last access master
Fixed default master
25.4.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No default
master suits low-power mode.
25.4.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to the last master that
performed an access request.
25.4.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the
last access master, the fixed master does not change unless the user modifies it by software (field FIXED_DEFMSTR of
the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration
registers (MATRIX_SCFGx), one for each slave, used to set a default master for each slave. MATRIX_SCFGx contains
the fields DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no
default, last access master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field selects a fixed default
master, provided that DEFMSTR_TYPE is set to fixed default master. Refer to Table 25-4, “Register Mapping”.
25.5 Arbitration
The Bus Matrix provides an arbitration technique that reduces latency when conflicting cases occur; for example, when
two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided to arbitrate
each slave differently.
The Bus Matrix provides the user with two arbitration types for each slave:
1. Round-robin arbitration (default)
2. Fixed priority arbitration
The field ARBT of MATRIX_SCFG is used to select the type of arbitration.
2 Internal Flash X - X
3 External Bus Interface X X X
4 Peripheral Bridge X X
Table 25-3. Master to Slave Access