Datasheet

41
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
8.1.3.11 GPNVM Bits
The SAM4S16/S8/S4/S2 features two GPNVM bits. These bits can be cleared or set respectively through the commands
“Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC user interface.
The SAM4SA16/SD32/SD16 features three GPNVM bits (GPNVM from Flash0) that can be cleared or set respectively
through the "Clear GPNVM Bit" and "Set GPNVM Bit" commands of the EEFC0 User Interface. The GPNVM bits of the
SAM4SA16/SD16/SD32 are only available on Flash0. There is no GPNVM bit on Flash1. The GPNVM0 is the security
bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or FLASH. The SAM4SD32/16 embeds
an additional GPNVM bit, GPNVM2. GPNVM2 is used only to swap the Flash0 and Flash1. If GPNVM bit 2 is ENABLE,
the Flash1 is mapped at address 0x0040_0000 (Flash1 and Flash0 are continuous). If GPNVM bit 2 is DISABLE, the
Flash0 is mapped at address 0x0040_0000 (Flash0 and Flash1 are continuous).
8.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via
GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set
General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears
the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting ERASE clears the GPNVM
Bit 2 and thus selects the boot from bank 0 by default.
8.2 External Memories
The SAM4S features one External Bus Interface to provide an interface to a wide range of external memories and to any
parallel peripheral.
8.2.1 Static Memory Controller
 16-Mbyte Address Space per Chip Select
 8- bit Data Bus
 Word, Halfword, Byte Transfers
 Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
 Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
 Programmable Data Float Time per Chip Select
 External Wait Request
 Automatic Switch to Slow Clock Mode
 Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
 NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses
 Hardware Configurable number of chip selects from 1 to 4
 Programmable timing on a per chip select basis
Table 8-2. General-purpose Non volatile Memory Bits
GPNVMBit[#] Function
0 Security bit
1 Boot mode selection
2 Flash selection (Flash 0 or Flash 1)