Datasheet

358
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
20.5.1 EEFC Flash Mode Register
Name: EEFC_FMR
Address: 0x400E0A00 (0), 0x400E0C00 (1)
Access: Read/Write
Offset: 0x00
• FRDY: Ready Interrupt Enable
0: Flash Ready does not generate an interrupt.
1: Flash Ready (to accept a new command) generates an interrupt.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
Number of cycles for Read/Write operations = FWS+1
• SCOD: Sequential Code Optimization Disable
0: The sequential code optimization is enabled.
1: The sequential code optimization is disabled.
No Flash read should be done during change of this register.
• FAM: Flash Access Mode
0: 128-bit access in read mode only, to enhance access speed.
1: 64-bit access in read mode only, to enhance power consumption.
No Flash read should be done during change of this register.
• CLOE: Code Loop Optimization Enable
0: The opcode loop optimization is disabled.
1: The opcode loop optimization is enabled.
No Flash read should be done during change of this register.
31 30 29 28 27 26 25 24
–––––CLOE–FAM
23 22 21 20 19 18 17 16
–––––––SCOD
15 14 13 12 11 10 9 8
–––– FWS
76543210
–––––––FRDY