Datasheet

34
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal
to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the
peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset
pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as
logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal
operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100
ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a
PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing.
Refer to Section 11.2 “Peripheral Signal Multiplexing on I/O Lines” on page 46. Also, if the ERASE pin is used as a
standard I/O output, asserting the pin to low does not erase the Flash.
6.6 Anti-tamper Pins/Low-power Tamper Detection
WKUP0 and WKUP1 generic wake-up pins can be used as anti-tamper pins. Anti-tamper pins detect intrusion, for
example, into a housing box. Upon detection through a tamper switch, automatic, asynchronous and immediate clear of
registers in the backup area will be performed. Anti-tamper pins can be used in all power modes (back-
up/wait/sleep/active). Anti-tampering events can be programmed so that half of the General Purpose Backup Registers
(GPBR) are erased automatically. See "Supply Controller" section for further description.
RTCOUT0 and RTCOUT1 pins can be used to generate waveforms from the RTC in order to take advantage of the RTC
inherent prescalers while the RTC is the only powered circuitry (low-power mode, backup mode) or in any active mode.
Entering backup or low-power modes does not affect the waveform generation outputs. Anti-tampering pin detection can
be synchronized with this signal.