Datasheet

338
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
19. General-Purpose Backup Registers (GPBR)
19.1 Description
The System Controller embeds 8 General-purpose Backup registers.
It is possible to generate an immediate clear of the content of General-purpose Backup registers 0 to 3 (first half) if a
Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other
General-purpose Backup registers (second half) remains unchanged.
The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply Controller
module, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and LPDBC must be other than 0.
If a Tamper event has been detected, it is not possible to write to the General-purpose Backup registers while the
LPDBCS0 or LPDBCS1 flags are not cleared in the Supply Controller Status register SUPC_SR.
19.2 Embedded Characteristics
 8 32-bit General Purpose Backup Registers