Datasheet

272
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
When the WDRSTEN in the WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
Figure 14-6. Watchdog Reset
14.4.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descending
order:
 General Reset
 Backup Reset
 Watchdog Reset
 Software Reset
 User Reset
Particular cases are listed below:
 When in User Reset:
 A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
 A software reset is impossible, since the processor reset is being activated.
 When in Software Reset:
 A watchdog event has priority over the current state.
 The NRST has no effect.
 When in Watchdog Reset:
 The processor reset is active and so a Software Reset cannot be programmed.
 A User Reset cannot be entered.
14.4.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
 RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP
Any
XXX
0x2 = Watchdog Reset