Datasheet

220
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
This is part of “UFSR: Usage Fault Status Subregister” .
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and Control
Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
• DIVBYZERO: Divide by Zero Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the
divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR to 1. See “Configuration and Con-
trol Register” .