Datasheet

211
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
12.9.1.8 System Handler Priority Registers
The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority.
They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and ignore
writes.
Table 12-33. System Fault Handler Priority Fields
Handler Field Register Description
Memory management fault (MemManage) PRI_4
System Handler Priority Register 1Bus fault (BusFault) PRI_5
Usage fault (UsageFault) PRI_6
SVCall PRI_11 System Handler Priority Register 2
PendSV PRI_14
System Handler Priority Register 3
SysTick PRI_15