Datasheet

197
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
12.8.3.6 Interrupt Priority Registers
Name: NVIC_IPRx [x=0..8]
Access: Read/Write
Reset: 0x000000000
The NVIC_IPR0–NVIC_IPR8 registers provide a 8-bit priority field for each interrupt. These registers are byte-accessible. Each
register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[34].
• PRI3: Priority (4m+3)
Priority, Byte Offset 3, refers to register bits [31:24].
• PRI2: Priority (4m+2)
Priority, Byte Offset 2, refers to register bits [23:16].
• PRI1: Priority (4m+1)
Priority, Byte Offset 1, refers to register bits [15:8].
• PRI0: Priority (4m)
Priority, Byte Offset 0, refers to register bits [7:0].
Notes: 1. Each priority field holds a priority value, 0–15. The lower the value, the greater the priority of the corresponding inter-
rupt. The processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes.
2. For more information about the IP[0] to IP[34] interrupt priority array, that provides the software view of the interrupt
priorities, see Table 12-29, “CMSIS Functions for NVIC Control” .
3. The corresponding IPR number n is given by n = m DIV 4.
4. The byte offset of the required Priority field in this register is m MOD 4.
31 30 29 28 27 26 25 24
PRI3
23 22 21 20 19 18 17 16
PRI2
15 14 13 12 11 10 9 8
PRI1
76543210
PRI0