Datasheet

1189
SAM4S Series [DATASHEET]
11100F–ATARM–22-Nov-13
Table 48-4. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History
Doc. Rev.
11100C Comments
Change
Request
Ref.
Introduction
In Section 2. “Block Diagram”, USB linked to Peripheral Bridge instead of AHB Bus Matrix in Figure 2-3, Figure
2-4, Figure 3. and Figure 2-2.
Reference to the LPM bit removed in the whole datasheet.
Flash rails mentioned in Section 5.1 “Power Supplies”.
Section 9. “Real Time Event Management” created.
WKUP[15:0] pins added on each block diagram in Section 2. “Block Diagram” and in Table 3-1, “Signal
Description List”.
All diagrams updated with Real Time Events in Section 2. “Block Diagram”.
JTAG and PA7 pins details added in Section 6.2.1 “Serial Wire JTAG Debug Port (SWJ-DP) Pins”.
8386
8392
8406
8439
8459
8484
8547
CORTEX
Section 12.8.3 “Nested Vectored Interrupt Controller (NVIC) User Interface”, offset information for NVIC register
mapping updated in Table 12-31, “Nested Vectored Interrupt Controller (NVIC) Register Mapping”.
Section 12.9.1 “System Control Block (SCB) User Interface”, deleted lines with MMFSR, BFSR, UFSR and
updated the note in Table 12-32, “System Control Block (SCB) Register Mapping”.
Table 12-34, “System Timer (SYST) Register Mapping”: table name updated (SysTick changed to SYST).
Harmonized instructions code fonts in Section 12.6 “Cortex-M4 Instruction Set”. Fixed various typos.
8211
8343
RTT
RTC 1Hz calibrated clock feature added in Section 15.1 “Description”, Section 15.4 “Functional Description”
and in RTT_MR register, see Section 15.5.1 “Real-time Timer Mode Register”.
RTC
New bullet “Safety/security features” added in Section 16.2 “Embedded Characteristics”. 8544
WDT
Note added in Section 17.5.3 “Watchdog Timer Status Register”. 8128
SUPC
Offsets updated and SYSC_WPMR in Table 18-1, “System Controller Registers”. Section 18.5.9 “System
Controller Write Protect Mode Register” added.
Force Wake Up Pin removed from Section 18.2 “Embedded Characteristics”.
In Section 18.4.3 “Voltage Regulator Control/Backup Low Power Mode”, removed informations related to WFE
and WFI, deleted reference to 1.8V for voltage regulator.
Figure 18-1 Block Diagram updated.
8253
8263
8363, 8407
8515
EEFC
In Section 20.5.2 “EEFC Flash Command Register”, table added in FCMD bitfield, details added in table in
FARG bitfield.
Note concerning bit number limitation added in
Section 20.4.3.5 “GPNVM Bit”.
8352
8390