Datasheet

1185
SAM4S Series [DATASHEET]
11100F–ATARM–22-Nov-13
Section 38. “High Speed MultiMedia Card Interface (HSMCI)”
Changed PDCFBYTE to FBYTE in Section 9.6 “WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation
using DMA Controller” and in Section 9.8 “READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using
DMA Controller”.
Section 14. “Register Write Protection”: changed title (was “Write Protection Registers”); revised content
In Section 15.2 “HSMCI Mode Register”, PDCMODE bit description, corrected reference to MCI Mode Register to
HSMCI Status Register.
In Section 15.7 “HSMCI Block Register”, BLKLEN bit description, removed sentence on its accessibility in HSMCI
Mode Register.
Section 15.18 “HSMCI Write Protection Mode Register”: modified register name (was HSMCI Write Protect Mode
Register); replaced list of protectable registers with cross-reference to section “Register Write Protection”
Section 15.19 “HSMCI Write Protection Status Register”: modified register name (was HSMCI Write Protect Status
Register) and updated description
Section 40. “USB Device Port (UDP)”
Section 40.2 “Embedded Characteristics”: replaced bullet “Integrated Pull-up on DP” with “Integrated Pull-up on
DPP”, added bullet “Integrated Pull-down on DDM”
Section 40.6.3.6 “Entering in Suspend State”: replaced “must drain less than 500uA” with “must drain no more than
2.5 mA”
Section 40.6.3 “Controlling Device States”: replaced “may not consume more than 500 µA” with “must not consume
more than 2.5 mA”
Table 40-6 ”Register Mapping”: corrected reset values for for UDP-FDR0..Y. Updated note
(1)
.
Section 40.4.2 “Power Management”: added detail on fast RC.
Changed register names:
 Section 40.7.10 old: UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints), new:
”UDP Endpoint Control and Status Register (CONTROL_BULK)”
 Section 40.7.11 old: UDP Endpoint Control and Status Register (Isochronous Endpoints), new: ”UDP
Endpoint Control and Status Register (ISOCHRONOUS)”.
Section 41. “Analog Comparator Controller (ACC)”
Section 41.1 “Description” Updated section for clarity.
Figure 41-1 ”Analog Comparator Controller Block Diagram”: Updated for clarity.
Section 41.6 “Functional Description”, Section 41.6.2 “Analog Settings” and Section 41.6.4 “Fault Mode”: Updated for
clarity.
Replaced section “Write Protection System” with Section 41.6.5 “Register Write Protection”. Updated Section 41.7.8
“ACC Write Protection Mode Register” and Section 41.7.9 “ACC Write Protection Status Register”. Bit 0 name in
Section 41.7.9 “ACC Write Protection Status Register” changed from WPROTERR to WPVS.
Section 42. “Analog-to-Digital Converter (ADC)”
Section 42.1 “Description”: Added sentence: The last channel is internally connected by a temperature sensor.
Section 42.2 “Embedded Characteristics”: updated section with new characteristics
Section 42.6.3 “Conversion Resolution”: Modified content to limit information on 12-bit resolution.
Section 42.6.14 “Register Write Protection”: Reworked content.
Section 42.7.3 “ADC Channel Sequence 1 Register” and Section 42.7.4 “ADC Channel Sequence 2 Register”:
modified max channel number to 15.
Section 42.7.12 “ADC Interrupt Status Register”: updated ‘ENDRX’ and ‘RXBUFF’ bit descriptions.
Section 42.7.15 “ADC Compare Window Register”: updated ‘LOWTHRES’ and ‘HIGHTHRES’ field descriptions.
Section 42.7.20 “ADC Write Protection Mode Register” and Section 42.7.21 “ADC Write Protection Status Register”:
Modified register names (from Write Protect to Write Protection). Reworked field descriptions.
Table 48-1. SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued)
Doc. Date Changes