Datasheet
1023
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0: No setup packet available.
1: A setup data packet has been sent by the host and is available in the FIFO.
Write:
0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1: No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully
received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx to the
microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.
Ensuing Data OUT transaction is not accepted while RXSETUP is set.
ISOERROR: A CRC error has been detected in an isochronous transfer
This flag generates an interrupt while it is set to one.
Read:
0: No error in the previous isochronous transfer.
1: CRC error has been detected, data available in the FIFO are corrupted.
Write:
0: Resets the ISOERROR flag, clears the interrupt.
1: No effect.
TXPKTRDY: Transmit Packet Ready
This flag is cleared by the USB device.
This flag is set by the USB device firmware.
Read:
0: There is no data to send.
1: The data is waiting to be sent upon reception of token IN.
Write:
0: Can be used in the procedure to cancel transmission data. (See Section 40.6.2.5 “Transmit Data Cancellation” on page 1001)
1: A new data payload has been written in the FIFO by the firmware and is ready to be sent.
This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the
FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx. Once the data payload has
been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start.
TXCOMP is set once the data payload has been received by the host.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.