Datasheet

76
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes
precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed
before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception
occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted,
irrespective of the exception number. However, the status of the new interrupt changes to pending.
12.4.3.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt
priority register entry into two fields:
 An upper field that defines the group priority
 A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt
exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the
handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are
processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ
number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see “Application Interrupt and
Reset Control Register” .
12.4.3.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is
higher than the priority of the exception being handled. See “Interrupt Priority Grouping” for more information about
preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” more
information.
Return
This occurs when the exception handler is completed, and:
 There is no pending exception with sufficient priority to be serviced
 The completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See
“Exception Return” for more information.
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception
that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception
handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception,
the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State
saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception
handler of the original exception enters the execute stage of the processor. On return from the exception handler of the
late-arriving exception, the normal tail-chaining rules apply.
Exception Entry