Datasheet

1083
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 43-2. Conversion Sequence
43.6.8 Register Write Protection
To prevent any single software error from corrupting <IP_acronym> behavior, certain registers in the
address space can be write-protected by setting the WPEN bit in the DACC Write Protection Mode
Register (DACC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the DACC Write Protection
Status Register (DACC_WPSR) is set and the field WPVSRC indicates the register in which the write
access has been attempted.
The WPVS bit is automatically cleared after reading the DACC_WPSR.
The following registers can be write-protected:
 DACC Mode Register
 DACC Channel Enable Register
 DACC Channel Disable Register
 DACC Analog Current Register
MCK
Write USER_SEL
field
Selected Channel
Write DACC_CDR
DAC Channel 0
Output
DAC Channel 1
Output
EOC
Read DACC_ISR
Select Channel 0
Channel 0 Channel 1
Data 0Data 1Data 2
Data 0Data 1
Data 2
Select Channel 1
None
TXRDY
CDR FIFO not full