Datasheet

1116
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
44.4.2.2 Wait Mode
Figure 44-9. Measurement Setup for Wait Mode
 VDDIO = VDDIN = 3.6V
 Core clock and master clock stopped
 Current measurement as shown in the above figure
 BOD disabled
 All peripheral clocks deactivated
Table 44-18 gives current consumption in typical conditions.
Table 44-17. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with
FAST RC
Sleep Mode
Consumption
Typical Value
@25°C
Core Clock/MCK (MHz)
VDDCORE Consumption
(AMP1)
Total Consumption
(AMP2) Unit
12 1.1 1.8 mA
80.81.2mA
40.40.7mA
20.30.7mA
10.20.5mA
0.5 0.2 0.5 mA
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2