Datasheet

937
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value
is taken into account.
Note: Changing the update period does make sense only if there is one or more synchronous channels and if the
update method 1 or 2 is selected (UPDM = 1 or 2 in “PWM Sync Channels Mode Register” ).
Figure 39-18. Synchronized Update of Update Period Value of Synchronous Channels
39.6.5.5 Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see
Section 39.6.3 “PWM Comparison Units”).
To prevent unexpected comparison match, the user must use the “PWM Comparison x Value Update Register”
(PWM_CMPVUPDx) and the “PWM Comparison x Mode Update Register” (PWM_CMPMUPDx) to change respectively
the comparison values and the comparison configurations while the channel 0 is still enabled. These registers hold the
new values until the end of the comparison update period (when CUPRCNT is equal to CUPR in “PWM Comparison x
Mode Register” (PWM_CMPMx) and the end of the current PWM period, then update the values for the next period.
CAUTION:
The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx.
Note: If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two
updates, only the last written value are taken into account.
End of PWM period and
end of Update Period
of Synchronous Channels
PWM_SCUPUPD Value
User's
Writing
PWM_SCUP