Datasheet

505
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault
Output Clear Register (PMC_FOCR).
29.14 Programming Sequence
1. If the fast crystal oscillator is not required, PLL and Divider can be directly configured (Step 6.) else the fast crystal
oscillator must be started (Step 2.).
2. Enable the fast crystal oscillator:
The fast crystal oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register
(CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in the MOSCXTST
field in CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCXTS field in
the PMC_SR register to be set. This can be done either by polling MOSCXTS in the PMC_SR, or by waiting for the
interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in the PMC_IER.
3. Switch the MAINCK to the main crystal oscillator by setting MOSCSEL in CKGR_MOR.
4. Wait for the MOSCSELS to be set in PMC_SR to ensure the switchover is complete.
5. Check the main clock frequency:
This main clock frequency can be measured via the Main Clock Frequency Register (CKGR_MCFR).
Read the CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in
CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have been
counted during a period of 16 slow clock cycles.
If MAINF = 0, switch the MAINCK to the Fast RC Oscillator by clearing MOSCSEL in CKGR_MOR. If MAINF ≠ 0,
proceed to Step 6.
6. Set PLLx and Divider (if not required, proceed to Step 7.):
In the names PLLx, DIVx, MULx, LOCKx, PLLxCOUNT, and CKGR_PLLxR, ‘x’ represents A or B.
All parameters needed to configure PLLx and the divider are located in CKGR_PLLxR register.
The DIVx field is used to control the divider itself. This parameter can be programmed between 0 and 127. Divider
output is divider input divided by DIVx parameter. By default, DIVx field is set to 0 which means that the divider and
PLLx are turned off.
The MULx field is the PLLx multiplier factor. This parameter can be programmed between 0 and 62. If MULx is set
to 0, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency multiplied by (MULx +
1).
The PLLxCOUNT field specifies the number of slow clock cycles before the LOCKx bit is set in the PMC_SR after
CKGR_PLLxR has been written.
Once the CKGR_PLLxR register has been written, the user must wait for the LOCKx bit to be set in the PMC_SR.
This can be done either by polling LOCKx in the PMC_SR or by waiting for the interrupt line to be raised if the
associated interrupt source (LOCKx) has been enabled in the PMC_IER. All fields in CKGR_PLLxR can be pro-
grammed in a single write operation. If at some stage one of the following parameters, MULx or DIVx is modified,
the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set again. The user
must wait for the LOCKx bit to be set before using the PLLx output clock.
7. Select the master clock and processor clock
The master clock and the processor clock are configurable via the PMC_MCKR.
The CSS field is used to select the clock source of the master clock and processor clock dividers. By default, the
selected clock source is the main clock.
The PRES field is used to define the processor clock and master clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the
PRES value.