Datasheet

479
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
27.5 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the
user depending on the function and the desired peripheral.
Table 27-1. Register Mapping
Offset Register Name Access Reset
0x00 Receive Pointer Register PERIPH
(1)
_RPR Read/Write 0
0x04 Receive Counter Register PERIPH_RCR Read/Write 0
0x08 Transmit Pointer Register PERIPH_TPR Read/Write 0
0x0C Transmit Counter Register PERIPH_TCR Read/Write 0
0x10 Receive Next Pointer Register PERIPH_RNPR Read/Write 0
0x14 Receive Next Counter Register PERIPH_RNCR Read/Write 0
0x18 Transmit Next Pointer Register PERIPH_TNPR Read/Write 0
0x1C Transmit Next Counter Register PERIPH_TNCR Read/Write 0
0x20 Transfer Control Register PERIPH_PTCR Write-only 0
0x24 Transfer Status Register PERIPH_PTSR Read-only 0