Datasheet

436
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
26.7.1.1 8-bit NAND Flash
Hardware Configuration
Software Configuration
Perform the following configuration:
 Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS Register on the Bus Matrix
User Interface.
 Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting
to 1 the address bits A21 and A22 during accesses.
 NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be programmed in
peripheral mode in the PIO controller.
 Configure a PIO line as an input to manage the Ready/Busy signal.
 Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the
data bus width and the system bus frequency.
In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE don’t care”, connect
NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.
D6
D0
D3
D4
D2
D1
D5
D7
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
ALE
CLE
D[0..7]
3V3
3V3
2 Gb
TSOP48 PACKAGE
U1 K9F2G08U0MU1 K9F2G08U0M
WE
18
N.C
6
VCC
37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1
N.C
2
N.C
3
N.C
4
N.C
21
N.C
22
N.C
23
N.C
24
R/B
7
N.C
26
N.C
27
N.C
28
I/O0
29
N.C
34
N.C
35
VSS
36
PRE
38
N.C
39
VCC
12
VSS
13
ALE
17
N.C
11
N.C
10
N.C
14
N.C
15
CLE
16
N.C
25
N.C
33
I/O1
30
I/O3
32
I/O2
31
N.C
47
N.C
46
N.C
45
I/O7
44
I/O6
43
I/O5
42
I/O4
41
N.C
40
N.C
48
R2 10KR2 10K
C2
100NF
C2
100NF
R1
10K
R1
10K
C1
100NF
C1
100NF