Datasheet

421
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
25.5.2.2 Round-Robin arbitration with last access master
Round-robin arbitration with last access master is a biased round-robin algorithm used by Bus Matrix arbiters. It allows
the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the current
transfer, if no other master request is pending, the slave remains connected to the last master that performs the access.
Other non-privileged masters incur one latency cycle if they want to access the same slave. This technique can be used
for masters that mainly perform single accesses.
25.5.2.3 Round-Robin arbitration with fixed default master
Round-robin arbitration with fixed default master is an algorithm used by the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its
fixed default master. Every request attempted by the fixed default master does not incur latency, whereas other non-
privileged masters still incur one latency cycle. This technique can be used for masters that mainly perform single
accesses.
25.5.3 Fixed Priority Arbitration
The fixed priority arbitration algorithm is used by the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If requests from two or more masters are active at the
same time, the master with the highest priority is serviced first. If requests from two or more masters with the same
priority are active at the same time, the master with the highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority registers for slaves (MATRIX_PRAS and
MATRIX_PRBS).
25.6 System I/O Configuration
The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in system I/O mode (such as JTAG, ERASE,
USB, etc.) or as general-purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral mode or in PIO
mode (PIO_PER or PIO_PDR registers) in the PIO controller has no effect. However, the direction (input or output), pull-
up, pull-down and other mode control is still managed by the PIO controller.
25.7 Register Write Protection
To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “Write Protection Mode Register” (MATRIX_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the “Write Protection Status Register”
(MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading MATRIX_WPSR.
The following registers can be write-protected:
 “Bus Matrix Master Configuration Registers”
 “Bus Matrix Slave Configuration Registers”
 “Bus Matrix Priority Registers For Slaves”
 “System I/O Configuration Register”