Datasheet

289
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10
seconds for SECONDS[3:0] field in RTC_TIMR). In this case the TDERR is held high until a clear command is asserted
by TDERRCLR bit in RTC_SCCR.
16.5.6 Updating Time/Calendar
To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the
Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must
be set to update calendar fields (century, year, month, date, day).
The ACKUPD bit is automatically set within a second after setting the UPDTIM and/or UPDCAL bit (meaning one second
is the maximum duration of the polling or wait for interrupt period). Once ACKUPD is set, it is mandatory to clear this flag
by writing the corresponding bit in the RTC_SCCR, after which the user can write to the Time Register, the Calendar
Register, or both.
Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the RTC_CR.
When entering programming mode of the calendar fields, the time fields remain enabled. When entering the
programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the
calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be
updated before entering programming mode. In successive update operations, the user must wait at least one second
after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits again. This is done by waiting for the
SEC flag in the RTC_SR before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also
be cleared.