Datasheet

1183
SAM4S Series [DATASHEET]
11100F–ATARM–22-Nov-13
Section 20. “Enhanced Embedded Flash Controller (EEFC)”
Corrected partial programming boundary from 32-bit to 64-bit and reworked Section 20.4.3.2 “Write Commands” and
all sub-sections with figures Figure 20-7 Full Page Programming to Figure 20-9 Programming Bytes in the Flash.
In Section 20.4.3.3 “Erase Commands”, modified paragraph on Erase pages (EPA) and Erase sector (ES)
commands, as well as Table 20-4 ”FARG Field for EPA Command”. Added “small sector” text as limitations in Table
20-4 ”FARG Field for EPA Command”.
Added notes when FARG exceeds limits in Section 20.4.3.4 “Lock Bit Protection”.
Re-worked Section 20.4.3.5 “GPNVM Bit” and added title in Section 20.4.3.6 “Calibration Bit”.
In Section 20.5.2 “EEFC Flash Command Register”, changed the description of FARG field accordingly.
Replaced NVIC by “interrupt controller” everywhere in the document.
Section 23. “Cyclic Redundancy Check Calculation Unit (CRCCU)”
Section 23.1 “Description”: added sentence with information on CRCCU and data integrity check.
Section 23.2 “Embedded Characteristics”: removed bullet ‘Single AHB Master Interface’. Inserted two new bullets on
data integrity check and background task. Added note.
Modified access type of Section 23.7.7 “CRCCU DMA Interrupt Mask Register”.
Section 23.6.2 “Transfer Control Register”: updated IEN bit description
Section 23.6.3 “Transfer Reference Register”: replaced “compared with that register” with “compared with this field”
in REFCRC field description
Updated bit descriptions in Section 23.7.2 “CRCCU DMA Enable Register” to Section 23.7.6 “CRCCU DMA Interrupt
Disable Register”, in Section 23.7.8 “CRCCU DMA Interrupt Status Register”, in Section 23.7.9 “CRCCU Control
Register” and in Section 23.7.12 “CRCCU Interrupt Enable Register” to Section 23.7.15 “CRCCU Interrupt Status
Register”.
Section 27. “Peripheral DMA Controller (PDC)”
Replaced “on- and/or off-chip” with “target” in Section 27.1 “Description” and Section 27.4.2 “Memory Pointers”.
Added last paragraph to Section 27.4.1 “Configuration” specifying that the peripheral clock must be enabled for a
PDC transfer.
Section 28. “Clock Generator”
Added Section 28.5.5 “Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator”.
Section 29. “Power Management Controller (PMC)”
Reworked Section 29.11 “Fast Startup” and added Section 29.12 “Start-up from Embedded Flash”
Reworked Section 29.13 “Main Clock Failure Detector”.
Enhanced Section 29.14 “Programming Sequence”
Enhanced Section 29.14 “Programming Sequence”
Section 29.16 “Register Write Protection”: Changed section title and re-worked content. In Section 29.17.21 “PMC
Write Protection Mode Register” and Section 29.17.25 “PMC Peripheral Clock Status Register 1”: Changed register
names and modified bit and field descriptions.
Section 30. “Chip Identifier (CHIPID)”
Section 30.3.1 “Chip ID Register”: Modi
fied “ARCH: Architecture Identifier” bi
t description table to show only SAM4S.
Section 31. “Parallel Input/Output Controller (PIO)”
Section 31.5.14 “Register Write Protection”: Changed section title and revised content.
Section 31.7.46 “PIO Write Protection Mode Register”: Modified register name and aligned bit descriptions. Replaced
list of protectable registers with cross-reference to section “Register Write Protection”.
Section 31.7.47 “PIO Write Protection Status Register”: Modified register name and aligned bit descriptions.
Removed note.
Table 48-1. SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued)
Doc. Date Changes