Datasheet

1050
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
42.6.9 Input Gain and Offset
The ADC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset.
The Programmable Gain Amplifier can be set to gains of 1/2, 1, 2 and 4. The Programmable Gain Amplifier can be used
either for single ended applications or for fully differential applications.
If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Otherwise the parameters of
CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as shown in Table 42-6.
AD7 CH7
AD8 CH8
AD9 CH9
AD10 CH10
AD11 CH11
AD12 CH12
AD13 CH13
AD14 CH14
AD15 CH15
Table 42-5. Input Pins and Channel Number In Differential Mode
Input Pins Channel Number
AD0–AD1 CH0
AD2–AD3 CH2
AD4–AD5 CH4
AD6–AD7 CH6
AD8–AD9 CH8
AD10–AD11 CH10
AD12–AD13 CH12
AD14–AD15 CH14
Table 42-4. Input Pins and Channel Number in Single Ended Mode (Continued)
Input Pins Channel Number
Table 42-6. Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit.
GAIN[0:1] GAIN (DIFF = 0) GAIN (DIFF = 1)
00 1 0.5
01 1 1
10 2 2
11 4 2