Datasheet

993
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.6.14 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
 “ADC Mode Register” on page 996
 “ADC Channel Sequence 1 Register” on page 999
 “ADC Channel Sequence 2 Register” on page 1000
 “ADC Channel Enable Register” on page 1001
 “ADC Channel Disable Register” on page 1002
 “ADC Extended Mode Register” on page 1009
 “ADC Compare Window Register” on page 1010
 “ADC Channel Gain Register” on page 1011
 “ADC Channel Offset Register” on page 1012