Datasheet

890
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.9 PWM Sync Channels Mode Register
Name: PWM_SCM
Address: 0x40020020
Access: Read-write
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page 913 .
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in “PWM Sync Channels
Update Control Register” is set.
2. The update occurs when the Update Period is elapsed.
• PTRM: PDC Transfer Request Mode
• PTRCS: PDC Transfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
PTRCS PTRM – – UPDM
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – SYNC3 SYNC2 SYNC1 SYNC0
Value Name Description
0 MODE0 Manual write of double buffer registers and manual update of synchronous channels
(1)
1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels
(2)
2 MODE2
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous
channels
(2)
3 – Reserved
UPDM PTRM WRDY Flag and PDC Transfer Request
0x
The WRDY flag in “PWM Interrupt Status Register 2” on page 897 and the PDC transfer request
are never set to 1.
1x
The WRDY flag in “PWM Interrupt Status Register 2” on page 897 is set to 1 as soon as the
update period is elapsed, the PDC transfer request is never set to 1.
2
0
The WRDY flag in “PWM Interrupt Status Register 2” on page 897 and the PDC transfer request
are set to 1 as soon as the update period is elapsed.
1
The WRDY flag in “PWM Interrupt Status Register 2” on page 897 and the PDC transfer request
are set to 1 as soon as the selected comparison matches.