Datasheet

869
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
flag and the PDC transfer request with a comparison match (see Section 38.6.3 “PWM Comparison Units”), by the
fields PTRM and PTRCS in the PWM_SCM register.
 ENDTX: this flag is set to 1 when a PDC transfer is completed
 TXBUFE: this flag is set to 1 when the PDC buffer is empty (no pending PDC transfers)
 UNRE: this flag is set to 1 when the update period defined by the UPR field has elapsed while the whole data has
not been written by the PDC. It is reset to 0 when the PWM_ISR2 register is read.
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by these flags.
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the
PWM_SCM register.
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in the update period by the
PTRM bit and the PTRCS field in the PWM_SCM register (at the end of the update period or when a comparison
matches).
5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC registers
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write registers that need to be updated
(PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 10.
8. Set UPDULOCK to 1 in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDU-
LOCK is reset, go to Step 7. for new values.
10. If an update of the update period value is required, check first that write of a new update value is possible by poll-
ing the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2 register, else go to Step 13.
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous channels when the Update Period
is elapsed. Go to Step 10. for new values.
13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define a new PDC transfer in the
PDC registers for new duty-cycle values. Go to Step 5.