Datasheet

858
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.6.2 PWM Channel
38.6.2.1 Channel Block Diagram
Figure 38-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of six blocks:
 A clock selector which selects one of the clocks provided by the clock generator (described in Section 38.6.1 on
page 857).
 A counter clocked by the output of the clock selector. This counter is incremented or decremented according to the
channel configuration and comparators matches. The size of the counter is 16 bits.
 A comparator used to compute the OCx output waveform according to the counter value and the configuration.
The counter value can be the one of the channel counter or the one of the channel 0 counter according to SYNCx
bit in the “PWM Sync Channels Mode Register” on page 890 (PWM_SCM).
 A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels.
 A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external
power control switches safely.
 An output override block that can force the two complementary outputs to a programmed value (OOOHx/OOOLx).
 An asynchronous fault protection mechanism that has the highest priority to override the two complementary
outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to 0, 1).
38.6.2.2 Comparator
The comparator continuously compares its counter value with the channel period defined by CPRD in the “PWM Channel
Period Register” on page 922 (PWM_CPRDx) and the duty-cycle defined by CDTY in the “PWM Channel Duty Cycle
Register” on page 920 (PWM_CDTYx) to generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
 the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator
described in the previous section. This channel parameter is defined in the CPRE field of the “PWM Channel Mode
Register” on page 918 (PWM_CMRx). This field is reset at 0.
Comparator
x
Cl o ck
Se l e c t o r
Channel x
Dead-Time
Gen er at o r
Output
Override
OCx
DTOHx
DTOLx
Fa u l t
Protection
OOOHx
PWMHx
PWMLx
OOOLx
Counter
Channel x
Duty-Cycle
Per i o d
Update
Co u n t e r
Channel 0
MUX
SYN Cx
Dead-Time
Gen er at o r
Output
Override
OCy
DTOHy
DTOLy
Fa u l t
Protection
OOOHy
PWMHy
PWMLy
OOOLy
Channel y (= x+1)
MUX
MUX
2-bit gray
counter z
Comparator
y
from
Clock
Generator
from APB
Peripheral Bus
z = 0 (x = 0, y = 1),
z = 1 (x = 2, y = 3),
z = 2 (x = 4, y = 5),
z = 3 (x = 6, y = 7)