Datasheet

833
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.6 HSMCI Command Register
Name: HSMCI_CMDR
Address: 0x40000014
Access: Write-only
This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by
an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.
• CMDNB: Command Number
This is the command index.
• RSPTYP: Response Type
• SPCMD: Special Command
31 30 29 28 27 26 25 24
– – – – BOOT_ACK ATACS IOSPCMD
23 22 21 20 19 18 17 16
– – TRTYP TRDIR TRCMD
15 14 13 12 11 10 9 8
– – – MAXLAT OPDCMD SPCMD
76543210
RSPTYP CMDNB
Value Name Description
0 NORESP No response.
1 48_BIT 48-bit response.
2 136_BIT 136-bit response.
3 R1B R1b response type
Value Name Description
0 STD Not a special CMD.
1 INIT
Initialization CMD:
74 clock cycles for initialization sequence.
2 SYNC
Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
3 CE_ATA
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
command line.
4 IT_CMD
Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
5 IT_RESP
Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
6 BOR
Boot Operation Request.
Start a boot operation mode, the host processor can read boot data from the MMC device directly.
7 EBO
End Boot Operation.
This command allows the host processor to terminate the boot operation mode.