Datasheet
83
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16 -
UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 -
UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange -
UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange -
UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 -
UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 -
UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract -
UDIV {Rd,} Rn, Rm Unsigned Divide -
UMAAL RdLo, RdHi, Rn, Rm
Unsigned Multiply Accumulate Accumulate Long (32 x 32 + 32 +32),
64-bit result
-
UMLAL RdLo, RdHi, Rn, Rm
Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result
-
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit result -
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 -
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 -
UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange -
UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange -
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 -
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 -
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences -
USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate -
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q
UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE
UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add -
UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add -
UXTAH {Rd,} Rn, Rm,{,ROR #} Rotate, unsigned extend and Add Halfword -
UXTB {Rd,} Rm {,ROR #n} Zero extend a byte -
UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16 -
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword -
VABS.F32 Sd, Sm Floating-point Absolute -
VADD.F32 {Sd,} Sn, Sm Floating-point Add -
VCMP.F32 Sd, <Sm | #0.0>
Compare two floating-point registers, or one floating-point register
and zero
FPSCR
VCMPE.F32 Sd, <Sm | #0.0>
Compare two floating-point registers, or one floating-point register
and zero with Invalid Operation check
FPSCR
Table 12-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags