Datasheet

703
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 35-14. The sample pulse
rejection mechanism applies.
In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx
line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set
to one (Rx line is at level 1 if undriven).
Figure 35-14.Asynchronous Start Bit Detection
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then
three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the
same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-
synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into
NRZ data and passed to USART for processing. Figure 35-15 illustrates Manchester pattern mismatch. When incoming
data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a
lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing
the Control Register (US_CR) with the RSTSTA bit to 1. See Figure 35-16 for an example of Manchester error detection
during data phase.
Figure 35-15.Preamble Pattern Mismatch
Manchester
encoded
data
Txd
1234
Sampling
Clock
(16 x)
Start
Detection
Manchester
encoded
data
Txd
SFD DATA
Preamble Length is set to 8
Preamble Mismatch
invalid pattern
Preamble Mismatch
Manchester coding error