Datasheet

653

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Clock Synchronization in Write Mode

The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not

detected, it is tied low until TWI_RHR is read.

Figure 33-29 on page 653 describes the clock synchronization in Read mode.

Figure 33-29.Clock Synchronization in Write Mode

Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different

from SADR.

2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the

mechanism is finished.

Rd DATA 0

Rd DATA 1

Rd DATA 2

SVACC

SVREAD

RXRDY

SCLWS

TXCOMP

DATA 1

DATA 2

SCL is stretched on the last bit of DATA1

As soon as a START is detected

TWCK

TWD

TWI_RHR

CLOCK is tied low by the TWI as long as RHR is full

DATA0 is not read in the RHR

ADRS SADR W ADATA0A A DATA 2DATA 1 S