Datasheet

643

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Figure 33-18.TWI Read Operation with Single Data Byte without Internal Address

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Transfer direction bit

Read ==> bit MREAD = 1

Start the transfer

TWI_CR = START STOP

Read status register

RXRDY = 1

Read Status register

TXCOMP = 1

END

BEGIN

Ye s

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Read Receive Holding Register