Datasheet
63
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
12.4.2.3 Behavior of Memory Accesses
The behavior of accesses to each region in the memory map is:
Note: 1. See “Memory Regions, Types and Attributes” for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use
the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to
occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more information, see “Memory
Protection Unit (MPU)” .
Additional Memory Access Constraints For Shared Memory
When a system includes shared memory, some memory regions have additional access constraints, and some regions
are subdivided, as Table 12-5 shows:
Table 12-4. Memory Access Behavior
Address Range Memory Region Memory
Type
XN Description
0x00000000 - 0x1FFFFFFF Code Normal
(1)
-
Executable region for program code. Data can also be
put here.
0x20000000 - 0x3FFFFFFF SRAM Normal
(1)
-
Executable region for data. Code can also be put here.
This region includes bit band and bit band alias areas,
see Table 12-6.
0x40000000 - 0x5FFFFFFF Peripheral Device
(1)
XN
This region includes bit band and bit band alias areas,
see Table 12-6.
0x60000000 - 0x9FFFFFFF External RAM Normal
(1)
- Executable region for data.
0xA0000000 - 0xDFFFFFFF External device Device
(1)
XN External Device memory
0xE0000000 - 0xE00FFFFF Private Peripheral Bus
Strongly-
ordered
(1)
XN
This region includes the NVIC, System timer, and
system control block.
0xE0100000 - 0xFFFFFFFF Reserved Device
(1)
XN Reserved
Table 12-5. Memory Region Shareability Policies
Address Range Memory Region Memory Type Shareability
0x00000000
-
0x1FFFFFFF
Code Normal
(1)
-
(2)
0x20000000
-
0x3FFFFFFF
SRAM Normal
(1)
-
(2)
0x40000000
-
0x5FFFFFFF
Peripheral Device
(1)
-
0x60000000
-
0x7FFFFFFF
External RAM Normal
(1)
-
WBWA
(2)
0x80000000
-
0x9FFFFFFF
WT
(2)