Datasheet

572
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 31-19.Time Slot Application Block Diagram
31.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
 “SSC Clock Mode Register” on page 575
 “SSC Receive Clock Mode Register” on page 576
 “SSC Receive Frame Mode Register” on page 578
 “SSC Transmit Clock Mode Register” on page 580
 “SSC Transmit Frame Mode Register” on page 582
 “SSC Receive Compare 0 Register” on page 586
 “SSC Receive Compare 1 Register” on page 586
SSC
RK
RF
RD
TD
TF
TK
SCLK
FSYNC
Data Out
Data in
CODEC
First
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data in
CODEC
Second
Time Slot
First Time Slot
Second Time Slot
Dstart
Dend