Datasheet

466
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Once all of the previous steps have been completed, the peripheral clocks can be enabled
and/or disabled via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.
28.2.14 Clock Switching Details
28.2.14.1Master Clock Switching Timings
Table 28-1 and Table 28-2 give the worst case timings required for the Master Clock to switch from
one selected clock to another one. This is in the event that the prescaler is de-activated. When the
prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be
added.
Notes: 1. PLL designates either the PLLA or the PLLB Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 28-1. Clock Switching Timings (Worst Case)
Fro
m Main Clock SLCK PLL Clock
To
Main
Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 28-2. Clock Switching Timings between Two PLLs (Worst Case)
Fro
m PLLA Clock PLLB Clock
To
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock
3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK