Datasheet

1081
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.11.6 SMC Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 50 pF
.
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables t
CPMCK
is MCK period. Timing extraction
43.11.6.1Read Timings
Table 43-51. SMC Read Signals - NRD Controlled (READ_MODE = 1)
Symbol Parameter Min Max Units
VDDIO Supply 1.8V
(2)
3.3V
(3)
1.8V
(2)
3.3V
(3)
NO HOLD Settings (NRD Hold = 0)
SMC
1
Data Setup before NRD High 19.9 17.9 — — ns
SMC
2
Data Hold after NRD High 0 0 — — ns
HOLD Settings (NRD Hold ≠ 0)
SMC
3
Data Setup before NRD High 16.0 14.0 ——ns
SMC
4
Data Hold after NRD High 00——ns
HOLD or NO HOLD Settings (NRD Hold ≠ 0, NRD Hold = 0)
SMC
5
A0 - A22 Valid before NRD High
(NRD setup +
NRD pulse) *
t
CPMCK
-6.5
(NRD setup +
NRD pulse)*
t
CPMCK
- 6.3
——ns
SMC
6
NCS Low before NRD High
(NRD setup +
NRD pulse -
NCS rd setup)
* t
CPMCK
- 4.5
(NRD setup +
NRD pulse -
NCS rd setup)
* t
CPMCK
- 5.1
——ns
SMC
7
NRD Pulse Width
NRD pulse *
t
CPMCK
- 7.2
NRD pulse *
t
CPMCK
- 6.2
——ns
Table 43-52. SMC Read Signals - NCS Controlled (READ_MODE = 0)
Symbol Parameter Min Max Units
VDDIO Supply 1.8V
(2)
3.3V
(3)
1.8V
(2)
3.3V
(3)
NO HOLD Settings (NCS rd Hold = 0)
SMC
8
Data Setup before NCS High 20.7 18.4 — — ns
SMC
9
Data Hold after NCS High 0 0 — — ns
HOLD Settings (NCS rd Hold ≠ 0)
SMC
10
Data Setup before NCS High 16.8 14.5 — — ns
SMC
11
Data Hold after NCS High 0 0 — — ns
HOLD or NO HOLD Settings (NCS rd Hold ≠ 0, NCS rd Hold = 0)