ARM-based Flash MCU SAM4S Series DATASHEET Description The Atmel SAM4S series is a member of a family of Flash microcontrollers based on the high-performance 32-bit ARM ® Cortex ® -M4 RISC processor. It operates at a maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with optional dual-bank implementation and cache memory, and up to 160 Kbytes of SRAM.
16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support System Embedded voltage regulator for single supply operation Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with failure detection and optional lowpower 32.
1.1 Configuration Summary The SAM4S series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the device family. Table 1-1.
2. Block Diagram TST UT System Controller Voltage Regulator PCK0-PCK2 PLLA PLLB PMC RC Osc 12/8/4 MHz XIN XOUT Flash Unique Identifier JTAG & Serial Wire User Signature In-Circuit Emulator 3-20 MHz Osc WKUP[15:0] VD DO VD DI N SE L JT AG TD TDI TMO TC S/S K/ WD SW IO CL K Figure 2-1.
TST UT System Controller Voltage Regulator PCK0-PCK2 PLLA PLLB PMC RC Osc 12/8/4 MHz XIN XOUT Flash Unique Identifier JTAG & Serial Wire User Signature In-Circuit Emulator 3-20 MHz Osc SUPC WKUP[15:0] VD DO VD DI N SE L JT AG TD TDI TMO TC S/S K/ WD SW IO CL K Figure 2-2.
UT VD DI N TST VD DO L SE JTA G TD TDI TMO TC S/S K/ W SW DI CL O K RT C RT OU CO T0 UT 1 Figure 2-3. SAM4SD32/SD16/SA16 100-pin version Block Diagram Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M In-Circuit Emulator 24-Bit N Cortex-M4 Processor SysTick Counter V Fmax 120 MHz I C DSP 3-20 MHz Osc.
TST System Controller PLLA PMC RC Osc 12/8/4 MHz XIN XOUT Cortex-M4 Processor Fmax 120 MHz SUPC 24-Bit N SysTick Counter V I DSP C MPU XIN32 XOUT32 Osc 32 kHz ERASE RC 32 kHz I VDDCORE RTT VDDPLL RTCOUT0 POR UT FLASH 2*1024 KBytes 2*512 KBytes 1024 KBytes DO SRAM 160 KBytes ROM 16 KBytes D CMCC (2 KB cache) 8 GPBREG VDDIO VD Flash Unique Identifier JTAG & Serial Wire In-Circuit Emulator 3-20 MHz Osc WKUP[15:0] VD Voltage Regulator PCK0-PCK2 PLLB DI N L SE JT AG TD TDI
3. Signal Description Table 3-1 gives details on signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.62V to 3.6V(4) VDDOUT Voltage Regulator Output Power 1.2V Output VDDPLL Oscillator and PLL Power Supply Power 1.
Table 3-1.
Table 3-1.
Table 3-1.
4. Package and Pinout SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 64- and 100-pin versions, and AT91SAM7S legacy products in 64-pin versions. 4.1 SAM4SD32/SD16/SA16/S16/S8C Package and Pinout 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm.
4.1.3 100-ball VFBGA Package Outline Figure 4-3.
4.1.4 100-lead LQFP Pinout Table 4-1.
4.1.5 100-ball TFBGA Pinout Table 4-2.
4.1.6 100-ball VFBGA Pinout Table 4-3.
4.2 SAM4SD32/SD16/SA16/S16/S8 Package and Pinout 4.2.1 64-lead LQFP Package Outline Figure 4-4. Orientation of the 64-lead LQFP Package 33 48 49 32 64 17 16 1 4.2.2 64-lead QFN Package Outline Figure 4-5. Orientation of the 64-lead QFN Package 64 1 48 16 33 17 4.2.3 49 TOP VIEW 32 64-ball WLCSP Package Outline Figure 4-6.
4.2.4 64-lead LQFP and QFN Pinout Table 4-4.
4.2.5 64-ball WLCSP Pinout Table 4-5.
5. Power Considerations 5.1 Power Supplies The SAM4S has several types of power supply pins: 5.2 VDDCORE pins: Power the core, the first flash rail and the embedded memories and peripherals. Voltage ranges from 1.08V to 1.32V. VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), the second flash rail, USB transceiver, Backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
For ADC, VDDIN needs to be greater than 2.0V. For DAC, VDDIN needs to be greater than 2.4V. Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V-3.6V) USB Transceivers. Can be the same supply ADC, DAC Analog Comp. VDDIN ADC, DAC, Analog Comparator Supply (2.0V-3.6V) VDDOUT Voltage Regulator VDDCORE VDDCORE Supply (1.08V-1.32V) VDDPLL Note: Restrictions For USB, VDDIO needs to be greater than 3.0V. For ADC, VDDIN needs to be greater than 2.0V. For DAC, VDDIN needs to be greater than 2.
5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The Power Management Controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low-power Modes The SAM4S has the following low-power modes: backup mode, wait mode and sleep mode.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered by setting the WAITMODE bit to 1 in the CKGR_MOR register in conjunction with FLPM = 0 or FLPM = 1 bits of the PMC_FSMR register or by the WFE instruction. The Cortex-M4 is able to handle external or internal events in order to wake-up the core.
5.5.4 Low-power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low-power modes. Table 5-1.
5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
5.7 Fast Start-up The SAM4S allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start-up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + USB + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-up signal to the Power Management Controller.
6. Input/Output Lines The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
Table 6-1. System I/O Configuration Pin List. SYSTEM_IO bit number Default function after reset Other function Constraints for normal start Low Level at startup Configuration (1) 12 ERASE PB12 10 DDM PB10 - 11 DDP PB11 - In Matrix User Interface Registers 7 TCK/SWCLK PB7 - 6 TMS/SWDIO PB6 - (Refer to the System I/O Configuration Register in the “Bus Matrix” section of the datasheet.
6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length.
7. Product Mapping Figure 7-1.
8. Memories 8.1 Embedded Memories 8.1.1 Internal SRAM The SAM4SD32 device (2x1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM. The SAM4SD16 device (2x512KBytes)embeds a total of 160-Kbytes high-speed SRAM. The SAM4SA16 device (1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM. The SAM4S16 device (1024 Kbytes) embeds a total of 128-Kbytes high-speed SRAM. The SAM4S8 device (512 Kbytes) embeds a total of 128-Kbytes high-speed SRAM.
Each Sector is organized in pages of 512 Bytes. For sector 0: The smaller sector 0 has 16 pages of 512Bytes The smaller sector 1 has 16 pages of 512 Bytes The larger sector has 96 pages of 512 Bytes From Sector 1 to n: The rest of the array is composed of 64-KByte sectors of 128 pages, each page of 512 bytes. Refer to Figure 8-2, "Flash Sector Organization" below. Figure 8-2.
Figure 8-3. Flash Size Flash 1 MBytes Flash 512 KBytes Flash 256 KBytes 2 * 8 KBytes 2 * 8 KBytes 2 * 8 KBytes 1 * 48 KBytes 1 * 48 KBytes 1 * 48 KBytes 3 * 64 KBytes 7 * 64 KBytes 15 * 64 KBytes Erasing the memory can be performed as follows: Note: Note: Note: On a 512-byte page inside a sector, of 8K Bytes EWP and EWPL commands can be only used in 8 KBytes sectors.
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.1.3.
bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or FLASH. The SAM4SD32/16 embeds an additional GPNVM bit: GPNVM2. This GPNVM bit is used only to swap the Flash0 and Flash1. If GPNVM bit 2 is: ENABLE: the Flash1 is mapped at address 0x0040_0000 (Flash1 and Flash0 are continuous). DISABLE: the Flash0 is mapped at address 0x0040_0000 (Flash0 and Flash1 are continuous). Table 8-2. 8.1.
9. Real Time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 9.1 Embedded Characteristics Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as ADC or DACC, for example, to start measurement/conversion without processor intervention.
9.2 Real Time Event Mapping List Table 9-1. Real Time Event Mapping List Event Generator Event Manager Function IO (WKUP0/1) General Purpose Backup Register (GPBR) Security / Immediate GPBR clear (asynchronous) on Tamper detection through WKUP0/1 IO pins.
10. System Controller The System Controller is a set of peripherals which allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... See the system controller block diagram in Figure 10-1 on page 39.
Figure 10-1.
10.1 System Controller and Peripheral Mapping Refer to Figure 7-1, "SAM4S Product Mapping". All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM4S embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO.
11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 11-1.
Table 11-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control 31 PWM X X Pulse Width Modulation 32 CRCCU X X CRC Calculation Unit 33 ACC X X Analog Comparator 34 UDP X X USB Device Port 11.
11.2.1 PIO Controller A Multiplexing Table 11-2.
11.2.2 PIO Controller B Multiplexing Table 11-3.
11.2.3 PIO Controller C Multiplexing Table 11-4.
SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 46
12. ARM Cortex-M4 12.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market.
12.
12.4 Cortex-M4 Models 12.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 12.4.1.1 Processor Modes and Privilege Levels for Software Execution The processor modes are: Thread mode Used to execute application software. The processor enters the Thread mode when it comes out of reset.
12.4.1.3 Core Registers Figure 12-2. Processor Core Registers R0 R1 R2 R3 Low registers R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL Table 12-2.
12.4.1.4 General-purpose Registers R0-R12 are 32-bit general-purpose registers for data operations. 12.4.1.5 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: 0 = Main Stack Pointer (MSP). This is the reset value. 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. 12.4.1.6 Link Register The Link Register (LR) is register R14.
12.4.1.8 Program Status Register Name: PSR Access: Read-write Reset: 0x000000000 31 N 30 Z 29 C 28 V 27 Q 26 23 22 21 20 25 24 T 19 18 17 16 12 11 10 9 – 8 ISR_NUMBER 4 3 2 1 0 ICI/IT – 15 14 13 ICI/IT 7 6 5 ISR_NUMBER The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR.
12.4.1.9 Application Program Status Register Name: APSR Access: Read-write Reset: 0x000000000 31 N 30 Z 23 22 29 C 28 V 27 Q 26 21 20 19 18 – 15 14 25 – 24 17 16 GE[3:0] 13 12 11 10 9 8 3 2 1 0 – 7 6 5 4 – The APSR contains the current state of the condition flags from previous instruction executions. • N: Negative Flag 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than.
12.4.1.10Interrupt Program Status Register Name: IPSR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 – 23 22 21 20 – 15 14 13 12 – 11 10 9 8 ISR_NUMBER 7 6 5 4 3 2 1 0 ISR_NUMBER The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
12.4.1.11 Execution Program Status Register Name: EPSR Access: Read-write Reset: 0x000000000 31 23 30 22 29 – 28 21 20 27 26 25 24 T ICI/IT 19 18 17 16 11 10 9 8 – 15 14 13 12 ICI/IT 7 6 5 – 4 3 2 1 0 – The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the InterruptibleContinuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
12.4.1.12Exception Mask Registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information. 12.4.1.
12.4.1.14Fault Mask Register Name: FAULTMASK Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FAULTMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). • FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI.
12.4.1.15Base Priority Mask Register Name: BASEPRI Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 BASEPRI The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. • BASEPRI Priority mask bits: 0x0000 = No effect.
12.4.1.16CONTROL Register Name: CONTROL Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 – 1 SPSEL 0 nPRIV – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. • SPSEL: Active Stack Pointer Defines the current stack: 0: MSP is the current stack pointer. 1: PSP is the current stack pointer.
12.4.1.17Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception Return” for more information. The NVIC registers control interrupt handling.
12.4.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. Figure 12-3. Memory Map 0xFFFFFFFF Vendor-specific memory 511MB Private peripheral 1.0MB bus External device 0xE0100000 0xE00FFFFF 0xE000 0000 0x DFFFFFFF 1.0GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.
Memory Types Normal The processor can re-order transactions for efficiency, or perform speculative reads. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. Strongly-ordered The processor preserves transaction order relative to all other transactions.
12.4.2.3 Behavior of Memory Accesses The behavior of accesses to each region in the memory map is: Table 12-4. Memory Access Behavior Address Range Memory Region Memory Type XN Description 0x00000000 - 0x1FFFFFFF Code Normal(1) - Executable region for program code. Data can also be put here. 0x20000000 - 0x3FFFFFFF SRAM Normal (1) - 0x40000000 - 0x5FFFFFFF Peripheral Device (1) XN This region includes bit band and bit band alias areas, see Table 12-6.
Table 12-5. Memory Region Shareability Policies (Continued) Address Range Memory Region 0xA00000000xBFFFFFFF Memory Type Shareability Shareable (1) External device Device (1) 0xC00000000xDFFFFFFF Non-shareable (1) 0xE00000000xE00FFFFF Private Peripheral Bus Strongly- ordered(1) Shareable (1) - 0xE01000000xFFFFFFFF Vendor-specific device Device (1) - - Notes: 1. 2. See “Memory Regions, Types and Attributes” for more information. WT = Write through, no write allocate.
Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6. Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table 127. Table 12-6. SRAM Memory Bit-banding Regions Address Range Memory Region 0x20000000- SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit-addressable through bit-band alias.
Figure 12-4.
Figure 12-5. Little-endian Format Memory 7 Register 0 31 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte 12.4.2.7 Synchronization Primitives The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
The processor removes its exclusive access tag if: It executes a CLREX instruction It executes a Store-Exclusive instruction, regardless of whether the write succeeds. An exception occurs. This means that the processor can resolve semaphore conflicts between different threads.
12.4.3 Exception Model This section describes the exception model. 12.4.3.1 Exception States Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active An exception is being serviced by the processor but has not completed.
An illegal unaligned access An invalid state on instruction execution An error on exception return. The following can cause a Usage Fault when the core is configured to report them: An unaligned address on word and halfword memory access A division by zero. SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.
For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 12-9 shows as having configurable priority, see: “System Handler Control and State Register” “Interrupt Clear-enable Registers” . For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” . 12.4.3.
On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the SCB_VTOR register to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see “Vector Table Offset Register” . 12.4.3.5 Exception Priorities As Table 12-9 shows, all exceptions have an associated priority, with: A lower priority value indicating a higher priority Configurable priorities for all exceptions except Reset, Hard fault and NMI.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” for more information. Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Late-arriving This mechanism speeds up preemption.
Figure 12-7. Exception Stack Frame ... Pre-IRQ top of stack {aligner} FPSCR S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 xPSR PC LR R12 R3 R2 R1 R0 Decreasing memory address IRQ top of stack Exception frame with floating-point storage ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Exception frame without floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 12-10.
Table 12-11. Faults (Continued) Fault Handler Attempt to access a coprocessor Bit Name Fault Status Register NOCP Undefined instruction UNDEFINSTR Attempt to enter an invalid instruction set state (1) INVSTATE Usage fault “UFSR: Usage Fault Status Subregister” Invalid EXC_RETURN value INVPC Illegal unaligned load or store UNALIGNED Divide By 0 DIVBYZERO Notes: 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled. 2.
Table 12-12.
12.5 Power Management The Cortex-M4 processor sleep modes reduce the power consumption: Sleep mode stops the processor clock Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” . This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 12.5.
12.6 Cortex-M4 Instruction Set 12.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions. Angle brackets, <>, enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix.
Table 12-13.
Table 12-13.
Table 12-13.
Table 12-13.
Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags VCVT.S32.F32 Sd, Sm Convert between floating-point and integer - VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point - VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding - VCVT.F32.F16 Sd, Sm Converts half-precision value to single-precision - VCVTT.F32.F16 Sd, Sm Converts single-precision register to half-precision - VDIV.
12.6.2 CMSIS Functions ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, the user might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 12-14.
12.6.3 Instruction Descriptions 12.6.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” . 12.6.3.
LSL #n logical shift left n bits, 1 ≤ n ≤ 31. LSR #n logical shift right n bits, 1 ≤ n ≤ 32. ROR #n rotate right n bits, 1 ≤ n ≤ 31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm. If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction.
If n is 32 or more, then all the bits in the result are cleared to 0. If n is 33 or more and the carry flag is updated, it is updated to 0. Figure 12-9. LSR #3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10.
RRX Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into bit[31] of the result. See Figure 12-12. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. Figure 12-12.RRX 12.6.3.
Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags.
Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 12-16.
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The example below shows instructions with the instruction width suffix. BCS.W label ; creates a 32-bit instruction even for a short ; branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction 12.6.4 Memory Access Instructions The table below shows the memory access instructions: Table 12-17.
12.6.4.1 ADR Load PC-relative address. Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. label is a PC-relative expression. See “PC-relative Expressions” . Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative.
12.6.4.2 LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms. Table 12-18.
LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rn is the register on which the memory address is based.
12.6.4.4 LDR and STR, Unprivileged Load and Store with unprivileged access. Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
12.6.4.5 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rt2 is the second register to load or store.
When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags.
register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details.
12.6.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional Execution” . reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
12.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based.
CMPEQ BNE .... R0, #0 try ; Did this succeed? ; No – try again ; Yes – we have the lock 12.6.4.9 CLREX Clear Exclusive. Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store.
12.6.5 General Data Processing Instructions The table below shows the data processing instructions: Table 12-20.
Table 12-20.
12.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: The user must not specify the S suffix The second operand must be a constant in the range 0 to 4095. Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before performing the calculation, making the base address for the calculation word-aligned.
12.6.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” .
12.6.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . Rd is the destination register.
12.6.5.4 CLZ Count Leading Zeros. Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the operand register. Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set and zero if bit[31] is set. Restrictions Do not use SP and do not use PC. Condition Flags This instruction does not change the flags.
CMP CMN CMPGT R2, R9 R0, #6400 SP, R7, LSL #2 12.6.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Operand2 is a flexible second operand.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set. Condition Flags If S is specified, these instructions: Update the N and Z flags according to the result Can update the C flag during the calculation of Operand2, see “Flexible Second Operand” Do not affect the V flag.
12.6.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the operand.
12.6.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SADD16 Performs two 16-bit signed integer additions. SADD8 Performs four 8-bit signed integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand.
12.6.5.10SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHADD16 Signed Halving Add 16. SHADD8 Signed Halving Add 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register.
12.6.5.11SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is any of: SHASX Add and Subtract with Exchange and Halving. SHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SHASX instruction: 1.
12.6.5.12SHSUB16 and SHSUB8 Signed Halving Subtract 16 and Signed Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHSUB16 Signed Halving Subtract 16. SHSUB8 Signed Halving Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register.
12.6.5.13SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SSUB16 Performs two 16-bit signed integer subtractions. SSUB8 Performs four 8-bit signed integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to change endianness of data: The SSUB16 instruction: 1.
12.6.5.14SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: op is any of: SASX Signed Add and Subtract with Exchange. SSAX Signed Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SASX instruction: 1.
12.6.5.15TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where cond is an optional condition code, see “Conditional Execution” . Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register.
12.6.5.16UADD16 and UADD8 Unsigned Add 16 and Unsigned Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UADD16 Performs two 16-bit unsigned integer additions. UADD8 Performs four 8-bit unsigned integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand.
12.6.5.17UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UASX Add and Subtract with Exchange. USAX Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UASX instruction: 1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
12.6.5.18UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHADD16 Unsigned Halving Add 16. UHADD8 Unsigned Halving Add 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the first operand. Rm is the register holding the second operand.
12.6.5.19UHASX and UHSAX Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UHASX Add and Subtract with Exchange and Halving. UHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UHASX instruction: 1.
12.6.5.20UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHSUB16 Performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
12.6.5.21SEL Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. Syntax SEL{}{} {,} , where: c, q are standard assembler syntax fields. Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation The SEL instruction: 1. Reads the value of each bit of APSR.GE. 2. Depending on the value of APSR.
12.6.5.22USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation The USAD8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the absolute values of the differences together. 3.
12.6.5.23USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Ra is the register that contains the accumulation value. Operation The USADA8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2.
12.6.5.24USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where op is any of: USUB16 Unsigned Subtract 16. USUB8 Unsigned Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register: The USUB16 instruction: 1.
12.6.6 Multiply and Divide Instructions The table below shows the multiply and divide instructions: Table 12-21.
12.6.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional Execution” . S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
12.6.6.2 UMULL, UMAAL, UMLAL Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMAAL Unsigned Long Multiply with Accumulate Accumulate. UMLAL Unsigned Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold the accumulating value.
12.6.6.3 SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLA Signed Multiply Accumulate Long (halfwords). X and Y specifies which half of the source registers Rn and Rm are used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
SMLABB SMLATB SMLATT SMLABT SMLABT SMLAWB SMLAWT R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R4, R3, R2 ; ; R10, R2, R5, R3 ; ; R10, R2, R1, R5 ; ; Multiplies bottom halfwords of R6 and R4, adds R1 and writes to R5 Multiplies top halfword of R6 with bottom halfword of R4, adds R1 and writes to R5 Multiplies top halfwords of R6 and R4, adds R1 and writes the sum to R5 Multiplies bottom halfword of R6 with top halfword of R4, adds R1 and writes to R5 Multiplies bottom halfwo
12.6.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra ; where: op is one of: SMLAD Signed Multiply Accumulate Dual. SMLADX Signed Multiply Accumulate Dual Reverse. X specifies which halfword of the source register Rn is used as the multiply operand. If X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution” .
12.6.6.5 SMLAL and SMLALD Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual. Syntax op{cond} RdLo, RdHi, Rn, Rm op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm where: op is one of: MLAL Signed Multiply Accumulate Long. SMLAL Signed Multiply Accumulate Long (halfwords, X and Y).
Restrictions In these instructions: Do not use SP and do not use PC. RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags.
Adds the signed accumulate value to the result of the subtraction. Writes the result of the addition to the destination register. The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords. This instruction: Optionally rotates the halfwords of the second operand. Performs two signed 16 × 16-bit halfword multiplications. Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
12.6.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where: op is one of: SMMLA Signed Most Significant Word Multiply Accumulate. SMMLS Signed Most Significant Word Multiply Subtract. If the X is omitted, the multiplications are bottom × bottom and top × top. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated.
SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits, ; subtracts R8, truncates and writes to R4. 12.6.6.8 SMMUL Signed Most Significant Word Multiply Syntax op{R}{cond} Rd, Rn, Rm where: op is one of: SMMUL Signed Most Significant Word Multiply. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted.
If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each operand.
If X is B, then the bottom halfword, bits [15:0] of Rn is used. If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot tom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used. SMULW{Y} Signed Multiply (word by halfword). Y specifies which halfword of the source register Rm is used as the second mul tiply operand. If Y is B, then the bottom halfword (bits [15:0]) of Rm is used.
12.6.6.11UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers.
12.6.6.12SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. Operation SDIV performs a signed integer division of the value in Rn by the value in Rm.
12.6.7 Saturating Instructions The table below shows the saturating instructions: Table 12-22.
12.6.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 31 for USAT.
12.6.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: op is one of: SSAT16 Saturates a signed halfword value to a signed range. USAT16 Saturates a signed halfword value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 15 for USAT.
12.6.7.3 QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: QADD Saturating 32-bit add. QADD8 Saturating four 8-bit integer additions. QADD16 Saturating two 16-bit integer additions. QSUB Saturating 32-bit subtraction. QSUB8 Saturating four 8-bit integer subtraction. QSUB16 Saturating two 16-bit integer subtraction. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
12.6.7.4 QASX and QSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QASX Add and Subtract with Exchange and Saturate. QSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The QASX instruction: 1.
12.6.7.5 QDADD and QDSUB Saturating Double and Add and Saturating Double and Subtract, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QDADD Saturating Double and Add. QDSUB Saturating Double and Subtract. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm, Rn are registers holding the first and second operands. Operation The QDADD instruction: Doubles the second operand value.
12.6.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn where: type is one of: UQASX Add and Subtract with Exchange and Saturate. UQSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UQASX instruction: 1.
12.6.7.7 UQADD and UQSUB Saturating Add and Saturating Subtract Unsigned. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: UQADD8 Saturating four unsigned 8-bit integer additions. UQADD16 Saturating two unsigned 16-bit integer additions. UDSUB8 Saturating four unsigned 8-bit integer subtractions. UQSUB16 Saturating two unsigned 16-bit integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
12.6.8 Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data: Table 12-23.
12.6.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} where: op is one of: PKHBT Pack Halfword, bottom and top with shift. PKHTB Pack Halfword, top and bottom with shift. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register Rm is the second operand register holding the value to be optionally shifted. imm is the shift length.
12.6.8.2 SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} where: op is one of: SXTB Sign extends an 8-bit value to a 32-bit value. SXTH Sign extends a 16-bit value to a 32-bit value. SXTB16 Sign extends two 8-bit values to two 16-bit values. UXTB Zero extends an 8-bit value to a 32-bit value. UXTH Zero extends a 16-bit value to a 32-bit value. UXTB16 Zero extends two 8-bit values to two 16-bit values.
Syntax op{cond} {Rd,} Rn, Rm {, ROR #n} op{cond} {Rd,} Rn, Rm {, ROR #n} where: op is one of: SXTAB Sign extends an 8-bit value to a 32-bit value and add. SXTAH Sign extends a 16-bit value to a 32-bit value and add. SXTAB16 Sign extends two 8-bit values to two 16-bit values and add. UXTAB Zero extends an 8-bit value to a 32-bit value and add. UXTAH Zero extends a 16-bit value to a 32-bit value and add. UXTAB16 Zero extends two 8-bit values to two 16-bit values and add.
12.6.9 Bitfield Instructions The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 12-24.
12.6.9.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation BFC clears a bitfield in a register.
12.6.9.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb.
12.6.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits.
12.6.10 Branch and Control Instructions The table below shows the branch and control instructions: Table 12-25.
12.6.10.1B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional Execution” . label is a PC-relative expression. See “PC-relative Expressions” . Rm is a register that indicates an address to branch to.
These instructions do not change the flags. Examples B BLE B.W BEQ BEQ.
12.6.10.2CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
12.6.10.3IT If-Then condition instruction. Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them. Condition Flags This instruction does not change the flags.
Restrictions The restrictions are: Rn must not be SP Rm must not be SP and must not be PC When any of these instructions is used inside an IT block, it must be the last instruction of the IT block. Condition Flags These instructions do not change the flags. Examples ADR.
12.6.11 Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions: Table 12-27.
12.6.11.1BKPT Breakpoint. Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
Examples CPSID CPSID CPSIE CPSIE i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) 12.6.11.3DMB Data Memory Barrier. Syntax DMB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation DMB acts as a data memory barrier.
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed. Condition Flags This instruction does not change the flags. Examples ISB ; Instruction Synchronisation Barrier 12.6.11.6MRS Move the contents of a special register to a general-purpose register.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored. Note: When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either: Rn is non-zero and the current BASEPRI value is 0 Rn is non-zero and less than the current BASEPRI value. See “MRS” . Restrictions Rn must not be SP and must not be PC. Condition Flags This instruction updates the flags explicitly based on the value in Rn.
12.6.11.10SVC Supervisor Call. Syntax SVC{cond} #imm where: cond is an optional condition code, see “Conditional Execution” . imm is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. Condition Flags This instruction does not change the flags.
12.7 Cortex-M4 Core Peripherals 12.7.1 Peripherals Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. See Section 12.8 ”Nested Vectored Interrupt Controller (NVIC)” System Control Block (SCB) The System Control Block (SCB) is the programmers model interface to the processor.
12.8 Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports: 1 to 35 interrupts. A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Level detection of interrupt signals. Dynamic reprioritization of interrupts. Grouping of priority values into group priority and subpriority fields. Interrupt tail-chaining.
12.8.2.1 NVIC Programming Hints The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 12-29.
12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface Table 12-31. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register Name Access Reset 0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read-write 0x00000000 ... ... ... ... ... 0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read-write 0x00000000 0XE000E180 Interrupt Clear-enable Register0 NVIC_ICER0 Read-write 0x00000000 ... ... ... ... ...
12.8.3.1 Interrupt Set-enable Registers Name: NVIC_ISERx [x=0..7] Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETENA 23 22 21 20 SETENA 15 14 13 12 SETENA 7 6 5 4 SETENA These registers enable interrupts and show which interrupts are enabled. • SETENA: Interrupt Set-enable Write: 0: No effect. 1: Enables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. Notes: 1.
12.8.3.2 Interrupt Clear-enable Registers Name: NVIC_ICERx [x=0..7] Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA These registers disable interrupts, and show which interrupts are enabled. • CLRENA: Interrupt Clear-enable Write: 0: No effect. 1: Disables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled.
12.8.3.3 Interrupt Set-pending Registers Name: NVIC_ISPRx [x=0..7] Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETPEND 23 22 21 20 SETPEND 15 14 13 12 SETPEND 7 6 5 4 SETPEND These registers force interrupts into the pending state, and show which interrupts are pending. • SETPEND: Interrupt Set-pending Write: 0: No effect. 1: Changes the interrupt state to pending. Read: 0: Interrupt is not pending.
12.8.3.4 Interrupt Clear-pending Registers Name: NVIC_ICPRx [x=0..7] Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRPEND 23 22 21 20 CLRPEND 15 14 13 12 CLRPEND 7 6 5 4 CLRPEND These registers remove the pending state from interrupts, and show which interrupts are pending. • CLRPEND: Interrupt Clear-pending Write: 0: No effect. 1: Removes the pending state from an interrupt. Read: 0: Interrupt is not pending.
12.8.3.5 Interrupt Active Bit Registers Name: NVIC_IABRx [x=0..7] Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACTIVE 23 22 21 20 ACTIVE 15 14 13 12 ACTIVE 7 6 5 4 ACTIVE These registers indicate which interrupts are active. • ACTIVE: Interrupt Active Flags 0: Interrupt is not active. 1: Interrupt is active. Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
12.8.3.6 Interrupt Priority Registers Name: NVIC_IPRx [x=0..8] Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI3 23 22 21 20 PRI2 15 14 13 12 PRI1 7 6 5 4 PRI0 The NVIC_IPR0-NVIC_IPR8 registers provide a 4-bit priority field for each interrupt. These registers are byte-accessible.
12.8.3.7 Software Trigger Interrupt Register Name: NVIC_STIR Access: Write-only Reset: 0x000000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INTID 7 6 5 4 3 2 1 0 INTID Write to this register to generate an interrupt from the software. • INTID: Interrupt ID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
12.9 System Control Block (SCB) The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions.
12.9.1 System Control Block (SCB) User Interface Table 12-32.
12.9.1.1 Auxiliary Control Register Name: SCB_ACTLR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 DISOOFP 8 DISFPCA 4 3 – 23 22 21 20 – 15 14 13 – 7 6 5 – 2 1 0 DISFOLD DISDEFWBUF DISMCYCINT The SCB_ACTLR register provides disable bits for the following processor functions: • IT folding • Write buffer use for accesses to the default memory map • Interruption of multi-cycle instructions.
12.9.1.2 CPUID Base Register Name: SCB_CPUID Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 19 18 25 24 17 16 9 8 1 0 Implementer 23 22 21 20 Variant 15 14 Constant 13 12 11 10 3 2 PartNo 7 6 5 PartNo 4 Revision The SCB_CPUID register contains the processor part number, version, and implementation information. • Implementer: Implementer Code 0x41: ARM. • Variant: Variant Number It is the r value in the rnpn product revision identifier: 0x0: Revision 0.
12.9.1.
• PENDSVCLR: PendSV Clear-pending Write: 0: No effect. 1: Removes the pending state from the PendSV exception. • PENDSTSET: SysTick Exception Set-pending Write: 0: No effect. 1: Changes SysTick exception state to pending. Read: 0: SysTick exception is not pending. 1: SysTick exception is pending. • PENDSTCLR: SysTick Exception Clear-pending Write: 0: No effect. 1: Removes the pending state from the SysTick exception. This bit is Write-only. On a register read, its value is Unknown.
12.9.1.4 Vector Table Offset Register Name: SCB_VTOR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 1 0 TBLOFF 23 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 TBLOFF 6 5 4 The SCB_VTOR register indicates the offset of the vector table base address from memory address 0x00000000. • TBLOFF: Vector Table Base Offset It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
12.9.1.5 Application Interrupt and Reset Control Register Name: SCB_AIRCR Access: Read-write Reset: 0x000000000 31 30 29 28 27 VECTKEYSTAT/VECTKEY 26 25 24 23 22 21 20 19 VECTKEYSTAT/VECTKEY 18 17 16 15 ENDIANNESS 14 13 9 PRIGROUP 8 7 6 12 11 10 4 3 2 – 5 – 1 VECTCLRACTI SYSRESETREQ VE 0 VECTRESET The SCB_AIRCR register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system.
Interrupt Priority Level Value, PRI_N[7:0] PRIGROUP Binary Point 0b101 (1) Number of Group Priority Bits Subpriority Bits Group Priorities Subpriorities bxx.yyyyyy [7:6] [5:0] 4 64 0b110 bx.yyyyyyy [7] [6:0] 2 128 0b111 b.yyyyyyy None [7:0] 1 256 Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field.
12.9.1.6 System Control Register Name: SCB_SCR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 SLEEPDEEP 1 SLEEPONEXIT 0 – – 23 22 21 20 – 15 14 13 12 – 7 6 – 5 4 SEVONPEND • SEVONPEND: Send Event on Pending Bit 0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
12.9.1.7 Configuration and Control Register Name: SCB_CCR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 STKALIGN 8 BFHFNMIGN 4 3 2 DIV_0_TRP UNALIGN_TRP – – 23 22 21 20 – 15 14 13 – 7 6 5 – 1 0 USERSETMPE NONBASETHR ND DENA The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore BusFaults.
If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • USERSETMPEND Enables unprivileged software access to the NVIC_STIR register, see “Software Trigger Interrupt Register” : 0: Disable. 1: Enable. • NONEBASETHRDENA: Thread Mode Enable Indicates how the processor enters Thread mode: 0: The processor can enter the Thread mode only when no exception is active.
12.9.1.8 System Handler Priority Registers The SCB_SHPR1-SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible. The system fault handlers and the priority field and register for each handler are: Table 12-33.
12.9.1.10System Handler Priority Register 2 Name: SCB_SHPR2 Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_11 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – • PRI_11: Priority Priority of system handler 11, SVCall. 12.9.1.
12.9.1.
1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • USGFAULTPENDED: Usage Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • SYSTICKACT: SysTick Exception Active Read: 0: The exception is not active. 1: The exception is active.
12.9.1.13Configurable Fault Status Register Name: SCB_CFSR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 DIVBYZERO 24 UNALIGNED 21 20 19 NOCP 18 INVPC 17 INVSTATE 16 UNDEFINSTR 13 12 STKERR 11 UNSTKERR 10 IMPRECISERR 9 PRECISERR 8 IBUSERR 5 MLSPERR 4 MSTKERR 3 MUNSTKERR 2 – 1 DACCVIOL 0 IACCVIOL – 23 22 – 15 BFRVALID 14 7 MMARVALID 6 – – • IACCVIOL: Instruction Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister” .
• MLSPERR: MemManage during Lazy State Preservation This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No MemManage fault occurred during the floating-point lazy state preservation. 1: A MemManage fault occurred during the floating-point lazy state preservation. • MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: The value in SCB_MMFAR is not a valid fault address.
• STKERR: Bus Fault on Stacking for Exception Entry This is part of “BFSR: Bus Fault Status Subregister” . 0: No stacking fault. 1: Stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the SCB_BFAR register.
• UNALIGNED: Unaligned Access Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . 0: No unaligned access fault, or unaligned access trapping not enabled. 1: The processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR register to 1. See “Configuration and Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
12.9.1.14Configurable Fault Status Register (Byte Access) Name: SCB_CFSR (BYTE) Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UFSR 23 22 21 20 UFSR 15 14 13 12 BFSR 7 6 5 4 MMFSR • MMFSR: Memory Management Fault Status Subregister The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section 12.9.1.13.
12.9.1.15Hard Fault Status Register Name: SCB_HFSR Access: Read-write Reset: 0x000000000 31 DEBUGEVT 30 FORCED 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 VECTTBL 0 – – 20 – 15 14 13 12 – 7 6 5 4 – The HFSR register gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
12.9.1.16MemManage Fault Address Register Name: SCB_MMFAR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The MMFAR register contains the address of the location that generated a memory management fault. • ADDRESS When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated the memory management fault.
12.9.1.17Bus Fault Address Register Name: SCB_BFAR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The BFAR register contains the address of the location that generated a bus fault. • ADDRESS When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus fault. Notes: 1.
12.10 System Timer (SysTick) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging, the counter does not decrement. The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops.
12.10.1.1SysTick Control and Status Name: SYST_CSR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 – 23 22 21 20 – 19 18 17 16 COUNTFLAG 15 14 13 12 11 10 9 8 3 2 CLKSOURCE 1 TICKINT 0 ENABLE – 7 6 5 4 The SysTick SYST_CSR register enables the SysTick features. • COUNTFLAG: Count Flag Returns 1 if the timer counted to 0 since the last time this was read. • CLKSOURCE: Clock Source Indicates the clock source: 0: External Clock. 1: Processor Clock.
12.10.1.2SysTick Reload Value Registers Name: SYST_RVR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 RELOAD 15 14 13 12 RELOAD 7 6 5 4 RELOAD The SYST_RVR register specifies the start value to load into the SYST_CVR register. • RELOAD Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0. The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF.
12.10.1.3SysTick Current Value Register Name: SYST_CVR Access: Read-write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT The SysTick SYST_CVR register contains the current value of the SysTick counter. • CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
12.10.1.4SysTick Calibration Value Register Name: SYST_CALIB Access: Read-write Reset: 0x000000000 31 NOREF 30 SKEW 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 20 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS The SysTick SYST_CSR register indicates the SysTick calibration properties. • NOREF: No Reference Clock It indicates whether the device provides a reference clock to the processor: 0: Reference clock provided. 1: No reference clock provided.
12.11 Memory Protection Unit (MPU) The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: Independent attribute settings for each region Overlapping regions Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines: Eight separate memory regions, 0-7 A background region.
The table below shows the encodings for the TEX, C, B, and S access permission bits. Table 12-35. TEX, C, B, and S Encoding TEX C B S Memory Type Shareability Other Attributes 0 0 x (1) Stronglyordered Shareable - 1 x (1) Device Shareable - Normal Not shareable 0 0 b000 1 Shareable 0 Not shareable Outer and inner write-through. No write allocate. 1 1 Normal 1 Shareable 0 0 0 Normal 1 x 0 x (1) 1 Reserved encoding - Implementation defined attributes.
Table 12-37 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 12-37.
STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; Region Attribute ; Enable ; Region Size and Enable The software must use memory barrier instructions: Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings After the MPU setup, if it includes memory transfers that must use the new MPU settings.
Use an STM instruction to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable 12.11.1.5Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” .
MPU Configuration for a Microcontroller Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows: Table 12-38.
12.11.2 Memory Protection Unit (MPU) User Interface Table 12-39.
12.11.2.1MPU Type Register Name: MPU_TYPE Access: Read-write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEPARATE – 23 22 21 20 IREGION 15 14 13 12 DREGION 7 6 5 4 – The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. • IREGION: Instruction Region Indicates the number of supported MPU instruction regions. Always contains 0x00.
12.11.2.2MPU Control Register Name: MPU_CTRL Access: Read-write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 PRIVDEFENA 1 HFNMIENA 0 ENABLE – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate. When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU is not implemented. The default memory map applies to accesses from both privileged and unprivileged software.
12.11.2.3MPU Region Number Register Name: MPU_RNR Access: Read-write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 REGION The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers. • REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
12.11.2.4MPU Region Base Address Register Name: MPU_RBAR Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 N 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR N-1 Note: 6 – 5 4 VALID REGION If the region size is 32B, the ADDR field is bits [31:5] and there is no Reserved field. The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR.
12.11.2.5MPU Region Attribute and Size Register Name: MPU_RASR Access: Read-write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
• SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.12 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort Aligned Banked register Base register A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned.
Exception service routine See “Interrupt handler” . Exception vector See “Interrupt vector” . Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address. Halfword A 16-bit data item. Illegal instruction An instruction that is architecturally Undefined. Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual implementations.
Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory” . Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents.
Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system. Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if debugging features of a processor. Word A 32-bit data item.
13. Debug and Test Features 13.1 Description The SAM4 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 13.
13.3 Application Examples 13.3.1 Debug Environment Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 13-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 13.3.
Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM4 Chip 2 Chip 1 SAM4-based Application Board In Test 13.4 Debug and Test Pin Description Table 13-1.
13.5 Functional Description 13.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kΩ,so that it can be left unconnected for normal operation.
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 13-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI - TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low.
CPI (all instruction cycles except for the first cycle) Interrupt overhead 13.5.6 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels: Software trace: Software can write directly to ITM stimulus registers.
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 13.5.7 IEEE® 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up, and must be kept in this state during the whole boundary scan operation.
13.5.8 ID Code Register Access: Read-only 31 30 29 28 27 21 20 19 PART NUMBER VERSION 23 22 15 14 13 PART NUMBER 7 6 5 12 11 4 3 MANUFACTURER IDENTITY 26 25 PART NUMBER 24 18 16 17 10 9 MANUFACTURER IDENTITY 2 1 8 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM4S 0x05B32 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1.
14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.
14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer periph_nreset: Affects the whole set of embedded peripherals nrst_out: Drives the NRST pin These reset signals are asserted by the Reset Controller, either on external events or on software action.
14.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
14.4.4.2 Backup Reset A Backup reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. The field RSTTYP in RSTC_SR is updated to report a Backup Reset. 14.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
14.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer PERRST: Writing PERRST at 1 resets all the embedded peripherals including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
14.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. If WDRPROC = 1, only the processor reset is asserted.
14.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: General Reset Backup Reset Watchdog Reset Software Reset User Reset Particular cases are listed below: When in User Reset: A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated.
14.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
14.5 Reset Controller (RSTC) User Interface Table 14-1.
14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1400 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1404 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1408 Access: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
15. Real-time Timer (RTT) 15.1 Description The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. It can be configured to be driven by the 1 Hz signal generated by the RTC, thus taking advantage of a calibrated 1 Hz clock.
The real-time 32-bit counter can also be supplied by the RTC 1 Hz clock. This mode is interesting when the RTC 1Hz is calibrated (CORRECTION field of RTC_MR register differs from 0) in order to guaranty the synchronism between RTC and RTT counters. Setting the RTC 1HZ clock to 1 in RTT_MR register allows to drive the 32-bit RTT counter with the RTC 1Hz clock. In this mode, RTTPRESC field has no effect. The Real-time Timer can also be used as a free-running timer with a lower time-base.
15.5 Real-time Timer (RTT) User Interface Table 15-1.
15.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1430 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 RTC1HZ 23 – 22 – 21 – 20 RTTDIS 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SCLK period.
15.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1434 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.5.
15.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E143C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
16. Real-time Clock (RTC) 16.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
16.3 Block Diagram Figure 16-1. RTC Block Diagram Slow Clock: SLCK 32768 Divider Time Wave Generator Date RTCOUT0 RTCOUT1 Clock Calibration APB 16.4 User Interface Entry Control Alarm Interrupt Control RTC Interrupt Product Dependencies 16.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 16.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller.
16.5 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar (or 1300 to 1499 in Persian mode). The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099.
The following checks are performed: 1. Century (check if it is in range 19 - 20 or 13-14 in Persian mode) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8.
Figure 16-2.
16.5.7 RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20-25°C).
32 Hz or 64 Hz can drive, for example, a TN LCD backplane signal while 1 Hz can be used to drive a blinking character like “:” for basic time display (hour, minute) on TN LCDs. Selection choice 5 provides a toggling signal when the RTC alarm is reached. Selection choice 6 provides a copy of the alarm flag, so the associated output is set high (logical 1) when an alarm occurs and immediately cleared when software clears the alarm interrupt source.
16.6 Real-time Clock (RTC) User Interface Table 16-1.
16.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1460 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters.
16.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1464 Access: Read-write 31 30 – – 23 22 – 29 28 27 TPERIOD 21 – 20 19 OUT1 15 14 13 26 12 11 24 THIGH 18 – HIGHPPM 25 17 16 OUT0 10 9 8 CORRECTION 7 6 5 4 3 2 1 0 – – – NEGPPM – – PERSIAN HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. • PERSIAN: PERSIAN Calendar 0 = Gregorian Calendar. 1 = Persian Calendar.
The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
Value Name Description 5 H_122US 122 μs 6 H_30US 30.5 μs 7 H_15US 15.
16.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1468 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
16.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E146C Access: Read-write 31 30 – – 23 22 29 28 27 14 25 24 18 17 16 DATE 21 20 19 DAY 15 26 MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (gregorian) or 13-14 (persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD).
16.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1470 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 6 5 SECEN Note: 11 MIN 4 3 SEC To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR register.
16.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1474 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 15 14 13 12 11 10 9 8 – – – – – – – – Note: 20 19 MONTH 7 6 5 4 3 2 1 0 – – – – – – – – To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made.
16.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1478 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 (FREERUN) = Time and calendar registers cannot be updated. 1 (UPDATE) = Time and calendar registers can be updated.
16.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E147C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect.
16.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1480 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERREN CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect.
16.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1484 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect.
16.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1488 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled.
16.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E148C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed.
17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 Embedded Characteristics 17.
running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. If the watchdog is restarted by writing into the WDT_CR register, the WDT_MR register must not be programmed during a period of time of 3 slow clock periods following the WDT_CR write access.
17.5 Watchdog Timer (WDT) User Interface Table 17-1.
17.5.1 Watchdog Timer Control Register Register Name: WDT_CR Address: 0x400E1450 Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
17.5.2 Watchdog Timer Mode Register Register Name: WDT_MR Address: x400E1454 Access Type: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
17.5.3 Watchdog Timer Status Register Register Name: WDT_SR Address: 0x400E1458 Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
18. Supply Controller (SUPC) 18.1 Description The Supply Controller (SUPC) controls the supply voltage of the Core of the system and manages the Backup Low Power Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention. Exit from this mode is possible on multiple wake-up sources including events on WKUP pins, or a Clock alarm. The SUPC also generates the Slow Clock by selecting either the Low Power RC oscillator or the Low Power Crystal oscillator. 18.
18.3 Block Diagram Figure 18-1.
18.4 Supply Controller Functional Description 18.4.
18.4.2 Slow Clock Generator The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 μs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
18.4.4 Supply Monitor The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply and which monitors VDDIO power supply. The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power supply drops below a certain level. The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV.
18.4.5 Backup Power Supply Reset 18.4.5.1 Raising the Backup Power Supply As soon as the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply Controller is entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is released, a counter is started for 5 slow clock cycles.
18.4.6 Core Reset The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described previously in Section 18.4.5 ”Backup Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. There are two additional sources which can be programmed to activate vddcore_nreset: a supply monitor detection a brownout detection 18.4.6.
Figure 18-4. Wake Up Sources SMEN sm_out RTCEN rtc_alarm RTTEN rtt_alarm LPDBC WKUPT1 RTCOUT0 LPDBCS1 LPDBCEN1 Low/High Level Detect Debouncer WKUPT0 LPDBC RTCOUT0 LPDBCEN0 LPDBCS0 Low/High Level Detect WKUPT0 WKUP0 WKUPEN0 Debouncer WKUPIS0 Low/High Level Detect WKUPDBC SLCK WKUPT1 Core Supply Restart WKUPEN1 WKUPS WKUPIS1 Debouncer WKUP1 Low/High Level Detect WKUPT15 WKUP15 WKUPEN15 WKUPIS15 Low/High Level Detect 18.4.7.
18.4.7.2 Low Power Debouncer Inputs It is possible to generate a waveform (RTCOUT0 and RTCOUT1) in all modes (including backup mode). It can be useful to control an external sensor and/or tampering function without waking up the processor. Please refer to the RTC section for waveform generation. Two separate debouncers are embedded for WKUP0 and WKUP1 inputs. The WKUP0 and/or WKUP1 inputs can be programmed to perform a wake up of the core power supply with a debouncing done by RTCOUT0.
Figure 18-6. Low Power Debouncer (Push-to-Break switch, pull-down resistors) AT91SAM RTCOUT0 WKUP0 WKUP1 Pull-Down Resistors GND GND GND The debouncing parameters can be adjusted and are shared (except the wake up input polarity) by both debouncers. The number of successive identical samples to wake up the core can be configured from 2 up to 8 in the LPDBC field of SUPC_WUMR. The period of time between 2 samples can be configured by programming the TPERIOD field in the RTC_MR register.
18.5 Supply Controller (SUPC) User Interface The User Interface of the Supply Controller is part of the System Controller User Interface. 18.5.1 System Controller (SYSC) User Interface Table 18-1.
18.5.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1410 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 VROFF 1 – 0 – • VROFF: Voltage Regulator Off 0 (NO_EFFECT) = no effect. 1 (STOP_VREG) = if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. • XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT) = no effect.
18.5.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1414 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH • SMTH: Supply Monitor Threshold Allows to select the threshold voltage of the supply monitor. Refer to electrical characteristics for voltage values.
18.5.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1418 Access: Read-write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 14 ONREG 13 BODDIS 12 BODRSTEN 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a brownout detection occurs.
18.5.6 Supply Controller Wake Up Mode Register Name: SUPC_WUMR Address: 0x400E141C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LPDBC 16 15 – 14 13 WKUPDBC 12 11 – 10 – 9 – 8 – 7 LPDBCCLR 6 LPDBCEN1 5 LPDBCEN0 4 – 3 RTCEN 2 RTTEN 1 SMEN 0 – • SMEN: Supply Monitor Wake Up Enable 0 (NOT_ENABLE) = the supply monitor detection has no wake up effect.
• WKUPDBC: Wake Up Inputs Debouncer Period Value Name Description 0 IMMEDIATE 1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods 6 Reserved Reserved 7 Reserv
18.5.
18.5.
• OSCSEL: 32-kHz Oscillator Selection Status 0 (RC) = the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 1 (CRYST) = the slow clock, SLCK is generated by the 32-kHz crystal oscillator. • LPDBCS0: Low Power Debouncer Wake Up Status on WKUP0 0 (NO) = no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 (PRESENT) = at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
18.5.9 System Controller Write Protect Mode Register Name: SYSC_WPMR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 • WPEN: 0: The Write Protection is disabled. 1: The Write Protection is enabled. • WPKEY: If a value is written in WPEN, the value is taken into account only if WPKEY is written with “RTC” (RTC written in ASCII Code, i.e. 0x525443 in hexadecimal).
19. General Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds Eight general-purpose backup registers. If a tamper event has been detected, it is not possible to write into general-purpose backup registers while the LPDBCS0 or LPDBCS1 flags are not cleared in supply controller status register SUPC_SR. 19.2 Embedded Characteristics 19.3 Eight 32-bit General Purpose Backup Registers General Purpose Backup Registers (GPBR) User Interface Table 19-1.
19.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1490 Access: Read-write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE • GPBR_VALUE: Value of GPBR x If a tamper event has been detected, it is not possible to write GPBR_VALUE while the LPDBCS0 or LPDBCS1 flags are not cleared in supply controller status register SUPC_SR.
20. Enhanced Embedded Flash Controller (EEFC) 20.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One 128-bit or 64-bit read buffer used for data read optimization. One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 MByte address space, so that each word can be written to its final address. Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane.
20.4.2.2 Code Read Optimization This feature is enabled if the EEFC_FMR register bit SCOD is cleared. A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential Code Fetch. Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization. The sequential code read optimization is enabled by default. If the bit SCOD in Flash Mode Register (EEFC_FMR) is set to 1, these buffers are disabled and the sequential code read is not optimized anymore.
When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken, and it becomes inefficient. In this case the loop code read optimization takes over from the sequential code read optimization to avoid insertion of wait states. The loop code read optimization is enabled by default. If in Flash Mode Register (EEFC_FMR), the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized anymore.
20.4.3 Flash Commands The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as programming the memory Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash erasing, etc. . Table 20-2.
Figure 20-6. Command State Chart Read Status: MC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: MC_FSR No Check if FRDY flag Set Yes Check if FLOCKE flag Set Yes Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successfull 20.4.3.1 Getting Embedded Flash Descriptor This command allows the system to learn about the Flash organization. The system can take full advantage of this information.
read operations to the EEFC_FRR register are done after the last word of the descriptor has been returned, then the EEFC_FRR register value is 0 until the next valid command. Table 20-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash Interface Description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes. FL_PLANE[0] 4 Number of bytes in the first plane. 4 + FL_NB_PLANE - 1 Number of bytes in the last plane.
Flash Error: at the end of the programming, the WriteVerify test of the Flash memory has failed. By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure 20-7 below). This mode is called Partial Programming. After any power-on sequence, the flash memory internal latch buffer is not initialized.
For the EPA command, the 2 lowest bits of the FARG field define the number of pages to be erased (FARG[1:0]): Table 20-4. FARG Field for EPA command: FARG[1:0] Number of pages to be erased with EPA command 0 4 pages 1 8 pages 2 16 pages 3 32 pages When the programming completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock region is locked. One error can be detected in the EEFC_FSR register after a programming sequence: Command Error: a bad keyword has been written in the EEFC_FCR register. Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. Note: Access to the Flash in read is permitted when a set, clear or get lock bit command is performed. 20.4.3.
20.4.3.6 Calibration Bit Calibration bits do not interfere with the embedded Flash memory plane. It is impossible to modify the calibration bits. The status of calibration bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is: Issue the Get CALIB Bit command by writing the Flash Command Register with GCALB (see Table 20-2). The FARG field is meaningless. Calibration bits can be read by the software application in the EEFC_FRR register.
20.4.3.9 User Signature Each part contains a User Signature of 512-bytes. It can be used by the user for storage. Read, write and erase of this area is allowed. To read the User Signature, the sequence is as follows: Send the Start Read User Signature command (STUS) by writing the Flash Command Register with the STUS command. When the User Signature is ready to be read, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) falls.
20.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0A00. Table 20-5.
20.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 (0), 0x400E0C00 (1) Access: Read-write Offset: 0x00 31 – 30 – 29 – 28 – 27 – 26 CLOE 25 – 24 FAM 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 SCOD 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 5 – 4 – 3 – 1 – 0 FRDY FWS 2 – • FRDY: Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt.
20.5.
• FARG: Flash Command Argument Erase all command Field is meaningless. Erase sector command FARG must be set with a page number that is in the sector to be erased. FARG[1:0] defines the number of pages to be erased.
20.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 (0), 0x400E0C08 (1) Access: Read-only Offset: 0x08 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FLERR 2 FLOCKE 1 FCMDE 0 FRDY • FRDY: Flash Ready Status 0: The Enhanced Embedded Flash Controller (EEFC) is busy. 1: The Enhanced Embedded Flash Controller (EEFC) is ready to start a new command.
20.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C (0), 0x400E0C0C (1) Access: Read-only Offset: 0x0C 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read.
21. Fast Flash Programming Interface (FFPI) 21.1 Description The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
Table 21-1.
Table 21-3. Command Bit Coding (Continued) DATA[15:0] Symbol Command Executed 0x0015 GLB Get Lock Bit 0x0034 SGPB Set General Purpose NVM bit 0x0044 CGPB Clear General Purpose NVM bit 0x0025 GGPB Get General Purpose NVM bit 0x0054 SSE Set Security Bit 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x001E GVE Get Version 21.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: Apply GND, VDDIO, VDDCORE and VDDPLL.
Table 21-4. Write Handshake Step Programmer Action Device Action Data I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latches MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Releases MODE and DATA signals Executes command and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input 21.2.4.
Table 21-5. Read Handshake (Continued) Step Programmer Action Device Action DATA I/O 10 Waits for NVALID high Sets DATA bus in input mode X 11 Sets DATA in output mode Sets NVALID signal Input 12 Sets NCMD signal Waits for NCMD high Input 13 Waits for RDY high Sets RDY signal Input 21.2.5 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21-3 on page 328.
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-7. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE WP or WPL or EWP or EWPL 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking DATA *Memory Address++ 5 Write handshaking DATA *Memory Address++ ... ... ... ...
Lock bits can be read using the Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 21-10. Get Lock Bit Command Step 1 Handshake Sequence Write handshaking MODE[3:0] DATA[15:0] CMDE GLB Lock Bit Mask Status 2 Read handshaking DATA 0 = Lock bit is cleared 1 = Lock bit is set 21.2.5.5 Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command also activates GP NVM bits.
Assert Erase during a period of more than 220 ms Power-off the chip Then it is possible to return to FFPI mode and check that Flash is erased. 21.2.5.7 Memory Write Command This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-14.
22. Cortex M Cache Controller (CMCC) (ONLY FOR SAM4SD32/SD16/SA16) 22.1 Description The Cortex M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, a tag directory, data memory, metadata memory and a configuration interface. 22.2 22.
22.4 Functional Description 22.4.1 Cache Operation On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated through the use of its configuration registers. The configuration interface is memory mapped in the private peripheral bus. Use the following sequence to enable the cache controller. 1.
22.5 Cortex M Cache Controller (CMCC) User Interface Table 22-1.
22.5.1 Cache Controller Type Register Name: CMCC_TYPE Address: 0x4007C000 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 12 CLSIZE 11 10 9 CSIZE 8 7 LCKDOWN 6 5 4 RRP 3 LRUP 2 RANDP 1 GCLK 0 AP WAYNUM • AP: Access Port Access Allowed 0: Access Port Access is disabled. 1: Access Port Access is enabled. • GCLK: Dynamic Clock Gating Supported 0: Cache controller does not support clock gating.
• LCKDOWN: Lock Down Supported 0: Lock Down is not supported. 1: Lock Down is supported.
22.5.2 Cache Controller Configuration Register Name: CMCC_CFG Address: 0x4007C004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 GCLKDIS • GCLKDIS: Disable Clock Gating 0: Clock gating is activated. 1: Clock gating is disabled.
22.5.3 Cache Controller Control Register Name: CMCC_CTRL Address: 0x4007C008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CEN • CEN: Cache Controller Enable 0: When set to 0, this field disables the cache controller. 1: When set to 1, this field enables the cache controller.
22.5.4 Cache Controller Status Register Name: CMCC_SR Address: 0x4007C00C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CSTS • CSTS: Cache Controller Status 0: When read as 0, this field indicates that the cache controller is disabled. 1: When read as 1, this field indicates that the cache controller is enabled.
22.5.5 Cache Controller Maintenance Register 0 Name: CMCC_MAINT0 Address: 0x4007C020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INVALL • INVALL: Cache Controller Invalidate All 0: No effect. 1: When set to one, this field invalidates all cache entries.
22.5.6 Cache Controller Maintenance Register 1 Name: CMCC_MAINT1 Address: 0x4007C024 Access: Write-only 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INDEX 7 6 5 4 3 – 2 – 1 – 0 – WAY INDEX • INDEX: Invalidate Index This field indicates the cache line that is being invalidated.
22.5.
22.5.8 Cache Controller Monitor Enable Register Name: CMCC_MEN Address: 0x4007C02C Access: Write-only Reset: 0x00002000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MENABLE • MENABLE: Cache Controller Monitor Enable 0: When set to 0, the monitor counter is disabled. 1: When set to 1, the monitor counter is activated.
22.5.9 Cache Controller Monitor Control Register Name: CMCC_MCTRL Address: 0x4007C030 Access: Write-only Reset: 0x00002000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Monitor 0: No effect. 1: When set to 1, this field resets the event counter register.
22.5.
23. Cyclic Redundancy Check Calculation Unit (CRCCU) 23.1 Description The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the Bus Matrix. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16. 23.2 23.3 Embedded Characteristics 32-bit cyclic redundancy check automatic calculation CRC calculation between two addresses of the memory CRCCU Block Diagram Figure 23-1.
23.4 Product Dependencies 23.4.1 Power Management The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the CRCCU in the PMC to enable the CRCCU clock. 23.4.2 Interrupt Source The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires programming the Interrupt Controller before configuring the CRCCU. 23.5 CRCCU Functional Description 23.5.
The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decremented if its value is different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In this case, the relevant CRCCU DMA Status Register bit, DMASR, is automatically cleared. If the COMPARE field of the CRCCU_MR register is set to true, the TR_CRC (Transfer Reference Register) is compared with the last CRC computed.
23.6.
23.6.
23.6.3 Transfer Reference Register Name: TR_CRC Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 REFCRC 23 22 21 20 REFCRC 15 14 13 12 REFCRC 7 6 5 4 REFCRC • REFCRC: Reference CRC When Compare mode is enabled, the checksum is compared with that register.
23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface Table 23-3.
23.7.1 CRCCU Descriptor Base Address Register Name: CRCCU_DSCR Address:0x40044000 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 3 – 2 – 1 – 8 – 0 – DSCR DSCR 15 14 13 7 – 6 – 5 – 12 DSCR 4 – • DSCR: Descriptor Base Address DSCR needs to be aligned with 512-byte boundaries.
23.7.2 CRCCU DMA Enable Register Name: CRCCU_DMA_EN Address:0x40044008 Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAEN • DMAEN: DMA Enable Register Write one to enable the CRCCU DMA channel.
23.7.
23.7.4 CRCCU DMA Status Register Name: CRCCU_DMA_SR Address:0x40044010 Access: Read-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMASR • DMASR: DMA Status Register When set to one, this bit indicates that DMA Channel is enabled.
23.7.5 CRCCU DMA Interrupt Enable Register Name: CRCCU_DMA_IER Address:0x40044014 Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIER • DMAIER: Interrupt Enable register Set bit to one to enable the interrupt.
23.7.6 CRCCU DMA Interrupt Disable Register Name: CRCCU_DMA_IDR Address:0x40044018 Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIDR • DMAIDR: Interrupt Disable register Set to one to disable the interrupt.
23.7.7 CRCCU DMA Interrupt Mask Register Name: CRCCU_DMA_IMR Address:0x4004401C Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIMR • DMAIMR: Interrupt Mask Register 0: Buffer Transfer Completed interrupt is disabled. 1: Buffer Transfer Completed interrupt is enabled.
23.7.8 CRCCU DMA Interrupt Status Register Name: CRCCU_DMA_ISR Address:0x40044020 Access: Read-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAISR • DMAISR: Interrupt Status register When DMAISR is set, DMA buffer transfer has terminated. This flag is reset after read.
23.7.9 CRCCU Control Register Name: CRCCU_CR Address:0x40044034 Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RESET • RESET: CRC Computation Reset When set to one, this bit resets the CRCCU_SR register to 0xFFFF FFFF.
23.7.10 CRCCU Mode Register Name: CRCCU_MR Address:0x40044038 Access: Read Write Reset: 31 – 23 – 15 – 7 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 DIVIDER 26 – 18 – 10 – 2 PTYPE 25 – 17 – 9 – 1 COMPARE 24 – 16 – 8 – 0 ENABLE • ENABLE: CRC Enable • COMPARE: CRC Compare If set to one, this bit indicates that the CRCCU DMA will compare the CRC computed on the data stream with the value stored. in the TR_CRC reference register.
23.7.11 CRCCU Status Register Name: CRCCU_SR Address:0x4004403C Access: Read-only Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRC CRC 15 14 13 12 7 6 5 4 CRC CRC • CRC: Cyclic Redundancy Check Value This register can not be read if the COMPARE field of the CRC_MR register is set to true.
23.7.
23.7.
23.7.
23.7.
24. SAM4S Boot Program 24.1 Description The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 24.2 Hardware and Software Constraints SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code.
24.4 Device Initialization Initialization follows the steps described below: 1. Stack setup 2. Setup the Embedded Flash Controller 3. External Clock detection (crystal or external clock on XIN) 4. If external crystal or clock with supported frequency, allow USB activation 5. Else, does not allow USB activation and use internal 12 MHz RC oscillator 6. Main oscillator frequency detection if no external clock detected 7. Switch Master Clock on Main Oscillator 8. C variable initialization 9.
24.5 SAM-BA Monitor The SAM-BA boot principle: Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table 24-2. Table 24-2.
Get Version (V): Return the SAM-BA boot version Output: ‘>’ 24.5.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product.
The Vendor ID (VID) is Atmel’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. For More details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB Implementers Forum: http://www.usb.org/developers/vendor/VID_Only_Form_withCCAuth_102407b.
24.5.4 In Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash.
25. Bus Matrix (MATRIX) 25.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 4 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
25.2.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table Table 25-3. Master to Slave Access Masters Slaves 25.
default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 25.5 Arbitration The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, allowing to arbitrate each slave differently.
There are three round-robin algorithm implemented: Round-Robin arbitration without default master Round-Robin arbitration with last access master Round-Robin arbitration with fixed default master 25.5.2.1 Round-Robin arbitration without default master This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner.
25.8 Bus Matrix (MATRIX) User Interface Table 25-4.
25.8.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0..MATRIX_MCFG3 Address: 0x400E0200 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 ULBT 0 • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
25.8.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0..MATRIX_SCFG4 Address: 0x400E0240 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 24 23 – 22 – 21 – 20 19 FIXED_DEFMSTR 18 17 16 DEFMSTR_TYPE 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 ARBT SLOT_CYCLE • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reach for a burst it may be broken by another master trying to access this slave.
25.8.3 Bus Matrix Priority Registers For Slaves Name: MATRIX_PRAS0..MATRIX_PRAS4 Address: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3], 0x400E02A0 [4] Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 – 14 – 13 12 11 – 10 – 9 7 – 6 – 5 3 – 2 – 1 M3PR 4 M1PR 24 – 16 M4PR 8 M2PR 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
25.8.4 System I/O Configuration Register Name: CCFG_SYSIO Address: 0x400E0314 Access Read-write Reset: 0x0000_0000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 SYSIO12 11 SYSIO11 10 SYSIO10 9 – 8 – 7 SYSIO7 6 SYSIO6 5 SYSIO5 4 SYSIO4 3 – 2 – 1 – 0 – • SYSIO4: PB4 or TDI Assignment 0 = TDI function selected. 1 = PB4 function selected. • SYSIO5: PB5 or TDO/TRACESWO Assignment 0 = TDO/TRACESWO function selected.
25.8.
25.8.6 Write Protect Mode Register Name: MATRIX_WPMR Address: 0x400E03E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – For more details on MATRIX_WPMR, refer to Section 25.7 “Write Protect Registers” on page 380. • WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
25.8.7 Write Protect Status Register Name: MATRIX_WPSR Address: 0x400E03E8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – For more details on MATRIX_WPSR, refer to Section 25.7 “Write Protect Registers” on page 380. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of MATRIX_WPMR.
26. Static Memory Controller (SMC) 26.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the Cortex-M4 based device. The External Bus Interface of the SAM4S consists of a Static Memory Controller (SMC). This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
26.3 I/O Lines Description Table 26-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWE Write Enable Signal Output Low A[23:0] Address Bus Output D[7:0] Data Bus NWAIT External Wait Signal NANDCS I/O Input Low NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low 26.4 Product Dependencies 26.4.
Figure 26-1. Memory Connections for Four External Devices NCS[0] - NCS[3] NRD SMC NWE A[23:0] D[7:0] NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable 24 8 26.6 A[23:0] D[7:0] Connection to External Devices 26.6.1 Data Bus Width The data bus width is 8 bits. Figure 26-2 shows how to connect a 512K x 8-bit memory on NCS0. Figure 26-2.
Figure 26-3. NAND Flash Signal Multiplexing on SMC Pins SMC NAND Flash Logic NCSx (activated if SMC_NFCSx=1) * NRD NANDOE NANDWE NANDOE NANDWE NWE * in CCFG_SMCNFCS Matrix register Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO Mode but only in peripheral mode (NWE function). If NWE function is not used for other external memories (SRAM, LCD), it must be configured in one of the following modes.
Figure 26-4. Standard and “CE don’t care” NAND Flash Application Examples D[7:0] D[7:0] AD[7:0] A[22:21] A[22:21] ALE CLE NCSx NCSx CE SMC NAND Flash “CE don t care” NAND Flash NANDOE NANDOE NOE NANDWE 26.7 ALE CLE Not Connected SMC AD[7:0] NOE NANDWE NWE PIO CE PIO R/B PIO NWE R/B Application Example 26.7.1 Implementation Examples Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for memory device availability.
26.7.1.1 8-bit NAND Flash Hardware Configuration Software Configuration Perform the following configuration: Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface. Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bits A21 and A22 during accesses. NANDOE and NANDWE signals are multiplexed with PIO lines.
26.7.1.2 NOR Flash Hardware Configuration D[0..7] A[0..
Figure 26-5. Standard Read Cycle MCK A[23:0] NRD NCS D[7:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NRD_HOLD NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE 26.8.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3.
26.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 26-6). Figure 26-6. No Setup, No Hold on NRD and NCS Read Signals MCK A[23:0] NRD NCS D[7:0] NRD_PULSE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE NRD_CYCLE 26.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1.
Figure 26-7. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[23:0] NRD NCS tPACC D[7:0] Data Sampling 26.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 26-8 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised.
26.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 26-9. The write cycle starts with the address setting on the memory address bus. 26.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3.
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 26.8.3.
Figure 26-11.WRITE_MODE = 1. The write operation is controlled by NWE MCK A[23:0] NWE NCS D[7:0] 26.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 26-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 26-12.WRITE_MODE = 0.
Section 26.15.4 ”SMC MODE Register” 26.8.6 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 404. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus.
Figure 26-13.Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[23:0] NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[7:0] Read to Write Wait State Chip Select Wait State 26.10.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state.
Figure 26-14.Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[23:0] NWE NRD no hold no setup D[7:0] write cycle Early Read wait state read cycle Figure 26-15.
Figure 26-16.Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[7:0] write cycle Early Read read cycle (WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1) 26.10.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
26.10.3.2Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 418). 26.10.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document.
26.11 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: before starting a read access to a different external memory before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select.
Figure 26-18.TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[23:0] NRD NCS tpacc D[7:0] TDF = 3 clock cycles NCS controlled read operation 26.11.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 26-19.TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[7:0] read access on NCS0 (NRD controlled) Read to Write Wait State write access on NCS0 (NWE controlled) 26.11.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins.
Figure 26-20.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[23:0] read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[7:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 26-21.
Figure 26-22.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[23:0] read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[7:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 26.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
26.12.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 26-23.
Figure 26-24.
26.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 26-25 and Figure 26-26. After deassertion, the access is completed: the hold step of the access is performed.
Figure 26-26.
26.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
26.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
Figure 26-29.Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[23:0] NWE 1 1 1 1 1 1 3 2 2 NCS NWE_CYCLE = 3 SLOW CLOCK MODE WRITE NWE_CYCLE = 7 SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State Figure 26-30.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 26-5. With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa) as shown in Figure 26-31.
Table 26-6. Programming of Read Timings in Page Mode Parameter Value Definition NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than the programmed value for tsa. 26.14.
26.15 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 26-7. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 26-7, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 26-7.
26.15.1 SMC Setup Register Name: SMC_SETUP[0..
26.15.2 SMC Pulse Register Name: SMC_PULSE[0..3] Address: 0x400E0004 [0], 0x400E0014 [1], 0x400E0024 [2], 0x400E0034 [3] Access: Read-write 31 – 30 29 28 27 NCS_RD_PULSE 26 25 24 23 – 22 21 20 19 NRD_PULSE 18 17 16 15 – 14 13 12 11 NCS_WR_PULSE 10 9 8 7 – 6 5 4 3 NWE_PULSE 2 1 0 • NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle.
26.15.3 SMC Cycle Register Name: SMC_CYCLE[0..3] Address: 0x400E0008 [0], 0x400E0018 [1], 0x400E0028 [2], 0x400E0038 [3] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 NRD_CYCLE 19 18 17 16 11 – 10 – 9 – 8 NWE_CYCLE 3 2 1 0 NRD_CYCLE 15 – 14 – 13 – 12 – 7 6 5 4 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
26.15.4 SMC MODE Register Name: SMC_MODE[0..3] Address: 0x400E000C [0], 0x400E001C [1], 0x400E002C [2], 0x400E003C [3] Access: Read-write 31 – 30 – 29 28 27 – 26 – 23 – 22 – 21 – 20 TDF_MODE 19 18 15 – 14 – 13 – 12 – 11 – 7 – 6 – 5 4 3 – PS EXNW_MODE 25 – 24 PMEN 17 16 10 – 9 – 8 – 2 – 1 WRITE_MODE 0 READ_MODE TDF_CYCLES • READ_MODE: 1: The read operation is controlled by the NRD signal.
• TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. • TDF_MODE: TDF Optimization 1: TDF optimization is enabled.
26.15.5 SMC OCMS Mode Register Name: SMC_OCMS Address: 0x400E0080 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CS3SE 18 CS2SE 17 CS1SE 16 CS0SE 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 - 0 SMSE • CSxSE: Chip Select (x = 0 to 3) Scrambling Enable 0: Disable Scrambling for CSx. 1: Enable Scrambling for CSx.
26.15.6 SMC OCMS Key1 Register Name: SMC_KEY1 Address: 0x400E0084 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 • KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values.
26.15.7 SMC OCMS Key2 Register Name: SMC_KEY2 Address: 0x400E0088 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 • KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values.
26.15.8 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0x400E00E4 Access: Read-write Reset: See Table 26-7 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
26.15.9 SMC Write Protect Status Register Name: SMC_WPSR Address: 0x400E00E8 Type: Read-only Value: See Table 26-7 31 — 30 — 29 — 28 — 23 22 21 20 27 — 26 — 25 — 24 — 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
27. Peripheral DMA Controller (PDC) 27.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
Table 27-1. Peripheral DMA Controller 27.3 Instance Name Channel T/R USART0 Receive ADC Receive SPI Receive SSC Receive HSMCI Receive Block Diagram Figure 27-1.
27.4 Functional Description 27.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
27.4.3 Transfer Counters Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer counter.
27.4.5 PDC Flags and Peripheral Status Register Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status Register. Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels. 27.4.5.
27.5 Peripheral DMA Controller (PDC) User Interface Table 27-2.
27.5.1 Receive Pointer Register Name: PERIPH_RPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
27.5.2 Receive Counter Register Name: PERIPH_RCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
27.5.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
27.5.4 Transmit Counter Register Name: PERIPH_TCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
27.5.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
27.5.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
27.5.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
27.5.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
27.5.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables PDC receiver channel requests if RXTDIS is not set.
27.5.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0 = PDC Receiver channel requests are disabled. 1 = PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = PDC Transmitter channel requests are disabled.
28. Power Management Controller (PMC) 28.1 Clock Generator 28.1.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 28.2.16 “Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 28.1.2 Embedded Characteristics The Clock Generator is made up of: A Low Power 32768 Hz Slow Clock Oscillator with bypass mode.
28.1.3 Block Diagram Figure 28-1. Clock Generator Block Diagram Clock Generator XTALSEL (Supply Controller) Embedded 32 kHz RC Oscillator 0 Slow Clock SLCK XIN32 XOUT32 32768 Hz Crystal Oscillator 1 MOSCSEL Embedded 4/8/12 MHz Fast RC Oscillator 0 Main Clock XIN XOUT MAINCK 3-20 MHz Crystal or Ceramic Resonator Oscillator 1 PLLA and Divider /2 PLLA Clock PLLACK PLLADIV2 PLLB and Divider /2 PLLB Clock PLLBCK PLLBDIV2 Status Control Power Management Controller 28.1.
28.1.4.1 Slow Clock RC Oscillator By default, the Slow Clock RC Oscillator is enabled and selected. The user has to take into account the possible drifts of the RC Oscillator. More details are given in the section “DC Characteristics” of the product datasheet. It can be disabled via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR). 28.1.4.2 Slow Clock Crystal Oscillator The Clock Generator integrates a 32768 Hz low-power oscillator.
28.1.5 Main Clock Figure 28-3 shows the Main Clock block diagram. Figure 28-3. Main Clock Block Diagram MOSCRCEN MOSCRCF MOSCRCS Fast RC Oscillator MOSCSELS MOSCSEL 0 MAINCK Main Clock MOSCXTEN 1 3-20 MHz Crystal or Ceramic Resonator Oscillator XIN XOUT MOSCXTST 3-20 MHz Oscillator Counter SLCK Slow Clock MOSCXTS MOSCRCEN MOSCXTEN RCMEAS MOSCSEL MAINCK Main Clock Ref.
When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. It is recommended to disable the Main Clock as soon as the processor no longer uses it and runs out of SLCK.
When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor. 28.1.5.4 Main Clock Oscillator Selection The user can select either the 12/8/4 MHz Fast RC Oscillator or the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source of Main Clock.
If MOSCSELS=0, the crystal oscillator can be disabled (MOSCXTEN=0 in the CKGR_MOR register). 28.1.5.6 Main Clock Frequency Counter The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
Figure 28-4. Dividers and PLL Blocks Diagram DIVB Divider B MAINCK MULB OUTB PLL B PLLBCK PLLBDIV2 DIVA Divider A MULA OUTA PLL A PLLACK PLLADIV2 PLLBCOUNT PLL B Counter LOCKB PLLACOUNT SLCK PLL A Counter LOCKA 28.1.6.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0.
Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR. Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR. Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR. Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER). Wait for LOCK flag in PMC_SR. Switch back to PLL by writing the appropriate value to CSS field of PMC_MCKR.
28.2 Power Management Controller (PMC) 28.2.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M4 Processor. The Supply Controller selects between the 32 kHz RC oscillator or the slow crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized.
28.2.3 Block Diagram Figure 28-5. General Clock Block Diagram Clock Generator Processor Clock Controller XTALSEL (Supply Controller) Sleep Mode Embedded 32 kHz RC Oscillator Divider /8 Slow Clock XOUT32 32768 Hz Crystal Oscillator SLCK 1 Prescaler /1, /2, /3, /4, /8, /16, /32, /64 MOSCSEL PLLACK CSS Master Clock MCK Peripherals Clock Controller (PMC_PCERx) 0 PRES ON/OFF Main Clock MAINCK 3-20 MHz Crystal or Ceramic Resonator Oscillator periph_clk[..
Figure 28-6. Master Clock Controller PMC_MCKR PMC_MCKR CSS PRES SLCK MAINCK Master Clock Prescaler PLLACK To the MCK Divider PLLBCK To the Processor Clock Controller (PCK) 28.2.5 Processor Clock Controller The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode Register (PMC_FSMR).
28.2.8 Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user can individually enable and disable the Clock on the peripherals. The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers.
Important: Prior to instructing the system to enter the Wait Mode, the internal sources of wake-up must be cleared. It must be verified that none of the enabled external wake-up inputs (WKUP) hold an active polarity. A Fast Start-up is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (WKUP) or upon an active alarm from the RTC, RTT and USB Controller. The polarity of the 16 wake-up inputs is programmable by writing the PMC Fast Start-up Polarity Register (PMC_FSPR).
The user interface does not provide any status for Fast Start-up, but the user can easily recover this information by reading the PIO Controller and the status registers of the RTC, RTT and USB Controller. 28.2.12 Main Crystal Clock Failure Detector The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
28.2.13 Programming Sequence 1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register (CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCXTS field in the PMC_SR register to be set.
Program the PRES field in PMC_MCKR. Wait for the MCKRDY bit to be set in PMC_SR. Program the CSS field in PMC_MCKR. Wait for the MCKRDY bit to be set in PMC_SR. If a new value for CSS field corresponds to Main Clock or Slow Clock, Program the CSS field in PMC_MCKR. Wait for the MCKRDY bit to be set in the PMC_SR. Program the PRES field in PMC_MCKR. Wait for the MCKRDY bit to be set in PMC_SR.
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR. 28.2.14 Clock Switching Details 28.2.14.1Master Clock Switching Timings Table 28-1 and Table 28-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated.
28.2.14.2Clock Switching Waveforms Figure 28-9. Switch Master Clock from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 28-10.
Figure 28-11.Change PLLx Programming Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Slow Clock Write CKGR_PLLxR Figure 28-12.
28.2.15 Write Protection Registers To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
28.2.16 Power Management Controller (PMC) User Interface Table 28-3.
Table 28-3. Register Mapping Note: Offset Register 0x010C Reserved 0x0110 Oscillator Calibration Register 0x130 PLL Maximum Multiplier Value Register Name Access Reset – – PMC_OCR Read-write 0x0040_4040 PMC_PMMR Read-Write 0x07FF07FF – If an offset is not listed in the table it must be considered as “reserved”.
28.2.16.1PMC System Clock Enable Register Name: PMC_SCER Address: 0x400E0400 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock (UDPCK) of the USB Device Port.
• PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 28.2.16.2PMC System Clock Disable Register Name: PMC_SCDR Address: 0x400E0404 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.3PMC System Clock Status Register Name: PMC_SCSR Address: 0x400E0408 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UDP: USB Device Port Clock Status 0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled.
28.2.16.4PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0x400E0410 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.5PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0x400E0414 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.6PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0x400E0418 Access: Read-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled.
28.2.16.7PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0x400E0420 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 CFDEN 24 MOSCSEL 23 22 21 20 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 WAITMODE 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 MOSCRCF 4 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • MOSCXTEN: Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT.
• MOSCRCF: Main On-Chip RC Oscillator Frequency Selection At start-up, the Main On-Chip RC Oscillator frequency is 4 MHz. Value Note: Name Description 0x0 12_MHz The Fast RC Oscillator Frequency is at 12 MHz (default) 0x1 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 0x2 4_MHz The Fast RC Oscillator Frequency is at 4 MHz MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR register. Therefore MOSCRCF and MOSCRCEN cannot be changed at the same time.
28.2.16.8PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0x400E0424 Access: Read-Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 RCMEAS 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.
28.2.16.9PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0x400E0428 Access: Read-write 31 – 30 – 29 ONE 28 – 27 – 26 25 MULA 24 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULA 15 – 14 – 13 7 6 5 12 11 PLLACOUNT 4 3 DIVA Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
28.2.16.10PMC Clock Generator PLLB Register Name: CKGR_PLLBR Address: 0x400E042C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 25 MULB 24 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULB 15 – 14 – 13 7 6 5 12 11 PLLBCOUNT 4 3 DIVB Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC. This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.11PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0430 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PLLBDIV2 12 PLLADIV2 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 – 1 0 CSS This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PLLBDIV2: PLLB Divisor by 2 PLLBDIV2 PLLB Clock Division 0 PLLB clock frequency is divided by 1. 1 PLLB clock frequency is divided by 2.
28.2.16.12PMC USB Clock Register Name: PMC_USB Address: 0x400E0438 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 – 0 USBS USBDIV 2 – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • USBS: USB Input Clock Selection 0 = USB Clock Input is PLLA.
28.2.16.13PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0440 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 1 CSS 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.
28.2.16.
28.2.16.16PMC Status Register Name: PMC_SR Address: 0x400E0468 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 FOS 19 CFDS 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 OSCSELS 6 – 5 – 4 – 3 MCKRDY 2 LOCKB 1 LOCKA 0 MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.
1 = Main on-chip RC oscillator is stabilized. • CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0 = A clock failure of the fast crystal oscillator clock is not detected. 1 = A clock failure of the fast crystal oscillator clock is detected.
28.2.16.
28.2.16.18PMC Fast Start-up Mode Register Name: PMC_FSMR Address: 0x400E0470 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 LPM 19 – 18 USBAL 17 RTCAL 16 RTTAL 15 FSTT15 14 FSTT14 13 FSTT13 12 FSTT12 11 FSTT11 10 FSTT10 9 FSTT9 8 FSTT8 7 FSTT7 6 FSTT6 5 FSTT5 4 FSTT4 3 FSTT3 2 FSTT2 1 FSTT1 0 FSTT0 FLPM This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.19PMC Fast Start-up Polarity Register Name: PMC_FSPR Address: 0x400E0474 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FSTP15 14 FSTP14 13 FSTP13 12 FSTP12 11 FSTP11 10 FSTP10 9 FSTP9 8 FSTP8 7 FSTP7 6 FSTP6 5 FSTP5 4 FSTP4 3 FSTP3 2 FSTP2 1 FSTP1 0 FSTP0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.2.16.20PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0478 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR • FOCLR: Fault Output Clear Clears the clock failure detector fault output.
28.2.16.21PMC Write Protect Mode Register Name: PMC_WPMR Address: 0x400E04E4 Access: Read-write Reset: See Table 28-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
28.2.16.22PMC Write Protect Status Register Name: PMC_WPSR Address: 0x400E04E8 Access: Read-only Reset: See Table 28-3 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register.
28.2.16.23PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0x400E0500 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • PIDx: Peripheral Clock x Enable 0 = No effect.
28.2.16.25PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0x400E0508 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – PID34 PID33 PID32 • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled.
28.2.16.26PMC Oscillator Calibration Register Name: PMC_OCR Address: 0x400E0510 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 SEL4 22 21 20 19 CAL4 18 17 16 15 SEL8 14 13 12 11 CAL8 10 9 8 7 SEL12 6 5 4 3 CAL12 2 1 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • CAL12: RC Oscillator Calibration bits for 12 MHz Calibration bits applied to the RC Oscillator when SEL12 is set.
SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 500
29. Chip Identifier (CHIPID) 29.1 Description Chip Identifier registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
29.3.1 Chip ID Register Name: CHIPID_CIDR Address: 0x400E0740 Access: Read-only 31 EXT 30 23 22 29 NVPTYP 28 21 20 27 26 19 18 ARCH 15 14 13 6 EPROC 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 3 2 VERSION • VERSION: Version of the Device Current version of the device.
Value Name 13 14 Description Reserved 2048K 15 2048 Kbytes Reserved • NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 5 Reserved 64K 6 7 64 Kbytes Reserved 128K 8 128 Kbytes Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 12 Reserved 1024K 13 14 1024 Kbytes Reserved 2048K 15 2048 Kbytes Reserved • SRAMSIZ: Internal SRAM Size Value Name Description 0 48K 48 Kbytes 1 192K 192 K
Value Name Description 13 256K 256 Kbytes 14 96K 96 Kbytes 15 512K 512 Kbytes • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x3C CM4P CM4P Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx A
Value Name Description 0x8A SAM4SxC SAM4SxC Series (100-pin version) 0x92 AT91x92 AT91x92 Series 0x93 SAM3NxA SAM3NxA Series (48-pin version) 0x94 SAM3NxB SAM3NxB Series (64-pin version) 0x95 SAM3NxC SAM3NxC Series (100-pin version) 0x99 SAM3SDxB SAM3SDxB Series (64-pin version) 0x9A SAM3SDxC SAM3SDxC Series (100-pin version) 0xA5 SAM5A SAM5A 0xB0 SAM4LxA SAM4LxA Series (48-pin version) 0xB1 SAM4LxB SAM4LxB Series (64-pin version) 0xB2 SAM4LxC SAM4LxC Series (100-pin versi
29.3.2 Chip ID Extension Register Name: CHIPID_EXID Address: 0x400E0744 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the EXT bit in CHIPID_CIDR is 0.
30. Parallel Input/Output (PIO) Controller 30.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
30.3 Block Diagram Figure 30-1. Block Diagram PIODCCLK Data PDC PIODC[7:0] Parallel Capture Mode Status PIODCEN1 PIODCEN2 Interrupt Controller PIO Interrupt PIO Clock PMC PIO Controller Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Table 30-1.
Figure 30-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control Command Driver On-Chip Peripherals PIO Controller Keyboard Driver 30.4 General Purpose I/Os External Devices Product Dependencies 30.4.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os.
30.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 30-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 30-3.
30.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers (PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in PIO_PDR. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. 30.5.
Figure 30-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 30.5.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
The filters also introduce some latencies, this is illustrated in Figure 30-5 and Figure 30-6. The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Additional Interrupt Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register).
Low Level on PIO line 3 High Level on PIO line 4 High Level on PIO line 5 Falling edge on PIO line 6 Rising edge on PIO line 7 Any edge on the other lines The configuration required is described below. 30.5.10.2Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 30.5.10.
30.5.13 Parallel Capture Mode 30.5.13.1Overview The PIO Controller integrates an interface able to read data from a CMOS digital image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous mode, etc.... For better understanding and to ease reading, the following description uses an example with a CMOS digital image sensor. 30.5.13.
the even or odd sensor data. If sensor data are numbered in the order that they are received with an index from 0 to n, if FRSTS = 0 then only data with an even index are sampled, if FRSTS = 1 then only data with an odd index are sampled. If data is ready in PIO_PCRHR and it is not read before a new data is stored in PIO_PCRHR, then an overrun error occurs. The previous data is lost and the OVRE flag in PIO_PCISR is set to 1. This flag is automatically reset when PIO_PCISR is read (reset after read).
Figure 30-12.Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=0) MCK PIODCCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR 0x6745_2301 RDATA (PIO_PCRHR) Figure 30-13.Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=1) MCK PIODCCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR RDATA (PIO_PCRHR) 0x7856_3412 30.5.13.
3. Write PIO_PCMR to set the PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the previous configuration. 4. Wait for a data ready by polling the DRDY flag in PIO_PCISR (“PIO Parallel Capture Interrupt Status Register” ) or by waiting the corresponding interrupt. 5. Check OVRE flag in PIO_PCISR. 6. Read the data in PIO_PCRHR (“PIO Parallel Capture Reception Holding Register” ). 7. If new data are expected go to step 4. 8.
30.6 “PIO Pad Pull Down Disable Register” on page 541 “PIO Pad Pull Down Status Register” on page 542 “PIO Parallel Capture Mode Register” on page 553 I/O Lines Programming Example The programing example as shown in Table 30-2 below is used to obtain the following configuration.
30.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 30-3.
Table 30-3.
Table 30-3.
30.7.1 PIO Enable Register Name: PIO_PER Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
30.7.3 PIO Status Register Name: PIO_PSR Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
30.7.5 PIO Output Disable Register Name: PIO_ODR Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
30.7.7 PIO Input Filter Enable Register Name: PIO_IFER Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
30.7.9 PIO Input Filter Status Register Name: PIO_IFSR Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line.
30.7.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line. 30.7.
30.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1. 30.7.
30.7.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0: No effect.
30.7.
30.7.
30.7.21 PIO Pull Up Disable Register Name: PIO_PUDR Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
30.7.23 PIO Pull Up Status Register Name: PIO_PUSR Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0: Pull Up resistor is enabled on the I/O line.
30.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
30.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
30.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select. 0: No Effect.
30.7.
30.7.
30.7.
30.7.
30.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0: Writing PIO_ODSR does not affect the I/O line.
30.7.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Disable. 0: No effect.
30.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection. 0: No effect. 1: The interrupt source is an Edge detection event. 30.
30.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt source selection. 0: The interrupt source is an Edge detection event.
30.7.43 PIO Rising Edge/High Level Select Register Name: PIO_REHLSR Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Rising Edge /High Level Interrupt Selection. 0: No effect.
30.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status. 0: The I/O line is not locked. 1: The I/O line is locked.
30.7.46 PIO Write Protect Mode Register Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC) Access: Read-write Reset: See Table 30-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – – – For more information on Write Protection Registers, refer to Section 30.7 ”Parallel Input/Output Controller (PIO) User Interface”.
30.7.47 PIO Write Protect Status Register Name: PIO_WPSR Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC) Access: Read-only Reset: See Table 30-3 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 – WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – – – • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
30.7.
30.7.49 PIO Parallel Capture Mode Register Name: PIO_PCMR Address: 0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – FRSTS HALFS ALWYS – 7 6 5 – – 4 DSIZE 3 2 1 0 – – – PCEN This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
30.7.
30.7.
30.7.
30.7.53 PIO Parallel Capture Interrupt Status Register Name: PIO_PCISR Address: 0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – RXBUFF ENDRX OVRE DRDY • DRDY: Parallel Capture Mode Data Ready 0: No new data is ready to be read since the last read of PIO_PCRHR.
30.7.54 PIO Parallel Capture Reception Holding Register Name: PIO_PCRHR Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDATA 23 22 21 20 RDATA 15 14 13 12 RDATA 7 6 5 4 RDATA • RDATA: Parallel Capture Mode Reception Data. if DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful. if DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful.
31. Synchronous Serial Controller (SSC) 31.1 Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
31.3 Block Diagram Figure 31-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 31.4 Application Block Diagram Figure 31-2.
31.5 Pin Name List Table 31-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 31.6 Type Product Dependencies 31.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
31.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
the transmitter clock the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 31.7.1.1 Clock Divider Figure 31-4.
Figure 31-6. Transmitter Clock Management TK (pin) Clock Output Tri_state Controller MUX Receiver Clock Divider Clock Data Transfer CKO CKS INV MUX Tri-state Controller CKI CKG Transmitter Clock 31.7.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
In addition, the maximum clock speed allowed on the TK pin is: Master Clock divided by 6 if Transmit Frame Synchro is input Master Clock divided by 2 if Transmit Frame Synchro is output 31.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 566.
Figure 31-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN RF RC0R SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start Start Selector RX Controller RD Receive Shift Register SSC_RCMR.STTDLY = 0 load SSC_RSHR load SSC_RFMR.FSLEN SSC_RHR Receiver Clock SSC_RFMR.DATLEN RX Controller counter reached STTDLY 31.7.
Figure 31-10.Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) TD (Output) B1 STTDLY BO X B1 STTDLY TD Start = Level Change on TF (Output) Start = Any Edge on TF BO BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 31-11.
31.7.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16.
Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. Table 31-4.
Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 31-15.Receive Frame Format in Continuous Mode Start = Enable Receiver Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN RD Note: 1. STTDLY is set to 0. 31.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR.
31.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 31-17.Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 31-18.
Figure 31-19.Time Slot Application Block Diagram SCLK TK FSYNC TF CODEC First Time Slot Data Out TD SSC Data in RD RF RK CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Second Time Slot Dend Serial Data Out Serial Data in 31.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
31.9 Synchronous Serial Controller (SSC) User Interface Table 31-5.
31.9.1 SSC Control Register Name: SSC_CR: Address: 0x40004000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
31.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0x40004004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV.
31.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0x40004010 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
31.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0x40004014 Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Receive Frame Sync Output Selection Value Name Description 0 NONE None, RF pin is an input 1 NEGATIVE Negative Pulse, RF pin is an output 2 POSITIVE Positive Pulse, RF pin is an output 3 LOW Driven Low during data transfer, RF pin is an output 4 HIGH Driven High during data transfer, RF pin is an output 5 TOGGLING Toggling at each start of data transfer, RF pin is an output • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN
31.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0x40004018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
31.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0x4000401C Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Transmit Frame Sync Output Selection Value Name Description 0 NONE None, TF pin is an input 1 NEGATIVE Negative Pulse, TF pin is an output 2 POSITIVE Positive Pulse,TF pin is an output 3 LOW TF pin Driven Low during data transfer 4 HIGH TF pin Driven High during data transfer 5 TOGGLING TF pin Toggles at each start of data transfer • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
31.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0x40004020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 31.9.
31.9.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Address: 0x40004030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 31.9.
31.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0x40004038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • CP0: Receive Compare Data 0 31.9.
31.9.13 SSC Status Register Name: SSC_SR Address: 0x40004040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
• RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register.
31.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0x40004044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect.
• RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt.
31.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0x40004048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect.
• RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt.
31.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0x4000404C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
• RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled.
31.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0x400040E4 Access: Read-write Reset: See Table 31-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
31.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0x400040E8 Access: Read-only Reset: See Table 31-5 31 — 30 — 29 — 28 — 23 22 21 20 27 — 26 — 25 — 24 — 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the SSC_WPSR register.
32. Serial Peripheral Interface (SPI) 32.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
32.3 Block Diagram Figure 32-1. Block Diagram PDC APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 32.4 Application Block Diagram Figure 32-2.
32.5 Signal Description Table 32-1. Signal Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 32.6 Product Dependencies 32.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
32.6.3 Interrupt The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI. Table 32-3. Peripheral IDs Instance ID SPI 21 32.6.4 Peripheral DMA Controller (PDC) The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full description of the PDC, refer to the corresponding section in the full datasheet. 32.7 Functional Description 32.7.
Figure 32-3 and Figure 32-4 show examples of data transfers. Figure 32-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 32-4.
32.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
32.7.3.1 Master Mode Block Diagram Figure 32-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
32.7.3.2 Master Mode Flow Diagram Figure 32-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
Figure 32-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 32-7.
Figure 32-8. PDC Status Register Flags Behavior 1 3 2 SPCK NPCS0 MOSI (from master) MISO (from slave) MSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB ENDTX ENDRX TXBUFE RXBUFF TXEMPTY 32.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
Figure 32-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 32.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register).
Transfer Size Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer's size it has to point to. The PDC will perform the following transfer size depending on the mode and number of bits per data. Fixed Mode: 8-bit Data: Byte transfer, PDC Pointer Address = Address + 1 byte, PDC Counter = Counter - 1 8-bit to 16-bit Data: 2 bytes transfer.
Figure 32-10.Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI Slave 0 Slave 1 Slave 14 NSS NSS SPI Master NSS NPCS0 NPCS1 NPCS2 NPCS3 1-of-n Decoder/Demultiplexer 32.7.3.
asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSNAAT bit (Chip Select Not Active After Transfer) at 1. This allows to de-assert systematically the chip select lines during a time DLYBCS.
32.7.3.10Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO controller).
Figure 32-12 shows a block diagram of the SPI when operating in Slave Mode. Figure 32-12.Slave Mode Functional Bloc Diagram SPCK NSS SPI Clock SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RDRF OVRES RD MSB Shift Register MISO SPI_TDR TD TDRE 32.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
32.8 Serial Peripheral Interface (SPI) User Interface Table 32-5.
32.8.1 SPI Control Register Name: SPI_CR Address: 0x40008000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
32.8.2 SPI Mode Register Name: SPI_MR Address: 0x40008004 Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
• LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
32.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0x40008008 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer.
32.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0x4000800C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
32.8.
• TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
32.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0x40008014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt.
32.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0x40008018 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt.
32.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0x4000801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
32.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0x40008030 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the defaults.
• BITS: Bits Per Transfer (See the (Note:) below the register table; Section 32.8.9 “SPI Chip Select Register” on page 624.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
Otherwise, the following equation determines the delay: × DLYBCTDelay Between Consecutive Transfers = 32 -----------------------------------MCK SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 626
32.8.
32.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0x400080E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the SPI_WPSR register.
33. Two-wire Interface (TWI) 33.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
33.3 List of Abbreviations Table 33-2. Abbreviations 33.4 Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 33-1.
33.5 Application Block Diagram Figure 33-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I C RTC I C LCD Controller I C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I C Standard 33.5.1 I/O Lines Description Table 33-3. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 33.6 Type Product Dependencies 33.6.
33.6.2 Power Management Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 33.6.3 Interrupt The TWI interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TWI. Table 33-5. Peripheral IDs 33.7 Instance ID TWI0 19 TWI1 20 Functional Description 33.7.
33.7.2 Modes of Operation The TWI has different modes of operations: Master transmitter mode Master receiver mode Multi-master transmitter mode Multi-master receiver mode Slave transmitter mode Slave receiver mode These modes are described in the following chapters. 33.8 Master Mode 33.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 33.8.2 Application Block Diagram Figure 33-5.
33.8.4 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte.
Figure 33-7. Master Write with Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent Figure 33-8.
33.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge.
33.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 33.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
Figure 33-12.Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A A IADR(15:8) IADR(7:0) Sr A DADR R A DATA N P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr W A IADR(7:0) A Sr R A DADR R A DATA N P One byte internal address TWD S DADR DADR DATA N P 33.8.6.
33.8.7.2 Data Receive with the PDC The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed without PDC to ensure that the exact number of bytes are received whatever the system bus latency conditions encountered during the end of buffer transfer period. 1. Initialize the receive PDC (memory pointers, transfer size - 2). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4.
Figure 33-15.
Figure 33-16.
Figure 33-17.
Figure 33-18.
Figure 33-19.
Figure 33-20.
33.9 Multi-master Mode 33.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 33-21.Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 33-22.
The flowchart shown in Figure 33-23 on page 648 gives an example of read and write operations in Multi-master mode. Figure 33-23.
33.10 Slave Mode 33.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 33.10.2 Application Block Diagram Figure 33-24.
33.10.4.2Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 33-26 on page 651. 33.10.4.
33.10.5.2Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
33.10.5.4Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 33-29 on page 653 describes the clock synchronization in Read mode. Figure 33-29.
33.10.5.5Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 33-30 on page 654 describes the repeated start + reversal from Read to Write mode. Figure 33-30.
33.10.6 Read Write Flowcharts The flowchart shown in Figure 33-32 on page 655 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 33-32.
33.11 Two-wire Interface (TWI) User Interface Table 33-6.
33.11.1 TWI Control Register Name: TWI_CR Address: 0x40018000 (0), 0x4001C000 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
• SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
33.11.
33.11.3 TWI Slave Mode Register Name: TWI_SMR Address: 0x40018008 (0), 0x4001C008 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
33.11.4 TWI Internal Address Register Name: TWI_IADR Address: 0x4001800C (0), 0x4001C00C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
33.11.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0x40018010 (0), 0x4001C010 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
33.11.6 TWI Status Register Name: TWI_SR Address: 0x40018020 (0), 0x4001C020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 33-25 on page 650, Figure 33-28 on page 652, Figure 33-30 on page 654 and Figure 33-31 on page 654. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
33.11.
33.11.
33.11.
33.11.
33.11.
34. Universal Asynchronous Receiver Transmitter (UART) 34.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with peripheral DMA controller (PDC) permits packet handling for these tasks with processor time reduced to a minimum. 34.2 Embedded Characteristics 34.
34.4 Product Dependencies 34.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 34-2. I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PA9 A UART0 UTXD0 PA10 A UART1 URXD1 PB2 A UART1 UTXD1 PB3 A 34.4.2 Power Management The UART clock is controllable through the Power Management Controller.
Figure 34-2. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 34.5.2 Receiver 34.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
Figure 34-4. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period URXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 34.5.2.3 Receiver Ready When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read. Figure 34-5.
Figure 34-7. Parity Error URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 34.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1. Figure 34-8.
Figure 34-9. Character Transmission Example: Parity enabled Baud Rate Clock UTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 34.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written character is transferred from UART_THR to the Shift Register.
34.5.5 Test Modes The UART supports three test modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register (UART_MR). The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to the UTXD line. The transmitter operates normally, but has no effect on the UTXD line. The Local Loopback mode allows the transmitted characters to be received.
34.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 34-3.
34.6.1 UART Control Register Name: UART_CR Address: 0x400E0600 (0), 0x400E0800 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
34.6.
34.6.
34.6.
34.6.
34.6.6 UART Status Register Name: UART_SR Address: 0x400E0614 (0), 0x400E0814 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
• TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active.
34.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0x400E0618 (0), 0x400E0818 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
34.6.8 UART Transmit Holding Register Name: UART_THR Address: 0x400E061C (0), 0x400E081C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
34.6.
35. Universal Synchronous Asynchronous Receiver Transmitter (USART) 35.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
35.3 Block Diagram Figure 35-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS DTR PMC Modem Signals Control MCK DIV DSR DCD MCK/DIV RI SLCK Baud Rate Generator SCK User Interface APB Table 35-1.
35.4 Application Block Diagram Figure 35-2. Application Block Diagram IrLAP PPP Modem Driver Serial Driver Field Bus Driver EMV Driver SPI Driver IrDA Driver USART RS232 Drivers RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers SPI Transceiver Modem PSTN 35.5 I/O Lines Description Table 35-2.
35.6 Product Dependencies 35.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
35.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Interrupt Controller.Using the USART interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 35-4. Peripheral IDs 35.7 Instance ID USART0 14 USART1 15 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications.
35.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
Table 35-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 35-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.
The modified architecture is presented below: Figure 35-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 Glitch-free Logic 3 FIDI >1 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 35.7.1.3 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 35-7. Table 35-7. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 35-8 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 35-8.
35.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled.
Figure 35-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 35.7.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1.
Figure 35-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width ALL_ONE Preamble Manchester encoded data Txd 8 bit width ALL_ZERO Preamble Manchester encoded data Txd 8 bit width ZERO_ONE Preamble Manchester encoded data Txd 8 bit width ONE_ZERO Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register.
Figure 35-10.Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur.
RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 35-14. The sample pulse rejection mechanism applies. In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set to one (Rx line is at level 1 if undriven). Figure 35-14.
Figure 35-16.Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported.
preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 35-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off.
Figure 35-20.Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 35.7.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set.
checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 35-9 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 35-9.
35.7.3.10Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed to zero no timeguard is generated.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received.
Table 35-11. Maximum Time-out Period (Continued) Baud Rate Bit Time Time-out 56000 18 1 170 57600 17 1 138 200000 5 328 35.7.3.12Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR).
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 35-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting.
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 729 and “PAR: Parity Type” on page 730.
Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION.
Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). Receive data 35.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 35-12. Table 35-12. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 μs 9.6 Kb/s 19.
Table 35-13. IrDA Baud Rate Error (Continued) Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.
35.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 35-36. Figure 35-36.
35.7.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.
Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted. Slave Select (NSS): This control line allows the master to select or deselect the slave. 35.7.8.1 Modes of Operation The USART can operate in SPI Master Mode or in SPI Slave Mode. Operation in SPI Master Mode is programmed by writing to 0xE the USART_MODE field in the Mode Register.
35.7.8.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave).
Figure 35-39.SPI Transfer Format (CPHA=0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 8 7 6 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 35.7.8.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 698. 35.7.8.
35.7.8.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
Figure 35-42.Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 35.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 35-43. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 35-43.Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 35.7.
35.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 35-16.
35.8.1 USART Control Register Name: US_CR Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” on page 727. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
35.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
• FCS: Force SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin).
35.8.3 USART Mode Register Name: US_MR Address: 0x40024004 (0), 0x40028004 (1) Access: Read-write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 CHMODE 7 NBSTOP 6 5 CHRL USCLKS 2 1 USART_MODE 0 This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• CHRL: Character Length. Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.
• CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
35.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0x40024004 (0), 0x40028004 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 18 – 17 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 7 6 5 4 3 2 1 USART_MODE CHRL USCLKS 0 This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
• CHMODE: Channel Mode Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • CPOL: SPI Clock Polarity – Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero.
35.8.5 USART Interrupt Enable Register Name: US_IER Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 736.
• CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable 0: No effect 1: Enables the corresponding interrupt.
35.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
35.8.7 USART Interrupt Disable Register Name: US_IDR Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 739.
• CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable 0: No effect 1: Disables the corresponding interrupt.
35.8.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
35.8.9 USART Interrupt Mask Register Name: US_IMR Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 742.
• CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
35.8.10 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
35.8.11 USART Channel Status Register Name: US_CSR Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 746.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• RI: Image of RI Input 0: RI is set to 0. 1: RI is set to 1. • DSR: Image of DSR Input 0: DSR is set to 0 1: DSR is set to 1. • DCD: Image of DCD Input 0: DCD is set to 0. 1: DCD is set to 1. • CTS: Image of CTS Input 0: CTS is set to 0. 1: CTS is set to 1. • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA.
35.8.12 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
35.8.13 USART Receive Holding Register Name: US_RHR Address: 0x40024018 (0), 0x40028018 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
35.8.14 USART Transmit Holding Register Name: US_THR Address: 0x4002401C (0), 0x4002801C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data.
35.8.15 USART Baud Rate Generator Register Name: US_BRGR Address: 0x40024020 (0), 0x40028020 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
35.8.16 USART Receiver Time-out Register Name: US_RTOR Address: 0x40024024 (0), 0x40028024 (1) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756. • TO: Time-out Value 0: The Receiver Time-out is disabled.
35.8.17 USART Transmitter Timeguard Register Name: US_TTGR Address: 0x40024028 (0), 0x40028028 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
35.8.18 USART FI DI RATIO Register Name: US_FIDI Address: 0x40024040 (0), 0x40028040 (1) Access: Read-write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
35.8.19 USART Number of Errors Register Name: US_NER Address: 0x40024044 (0), 0x40028044 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE=0x4 or 0x6 in “USART Mode Register” on page 729. • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer.
35.8.21 USART Manchester Configuration Register Name: US_MAN Address: 0x40024050 (0), 0x40028050 (1) Access: Read-write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• RX_PP: Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
35.8.22 USART Write Protect Mode Register Name: US_WPMR Address: 0x400240E4 (0), 0x400280E4 (1) Access: Read-write Reset: See Table 35-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
35.8.23 USART Write Protect Status Register Name: US_WPSR Address: 0x400240E8 (0), 0x400280E8 (1) Access: Read-only Reset: See Table 35-16 31 — 30 — 29 — 28 — 23 22 21 20 27 — 26 — 25 — 24 — 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
35.8.24 USART Version Register Name: US_VERSION Address: 0x400240FC (0), 0x400280FC (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 MFN 16 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 VERSION 2 VERSION • VERSION: Hardware Module Version Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. • MFN: Metal Fix Number Reserved. Value subject to change.
36. Timer Counter (TC) 36.1 Description The Timer Counter (TC) includes 3 identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
36.3 Quadrature decoder Advanced line filtering Position / revolution / speed 2-bit Gray Up/Down Counter for Stepper Motor Block Diagram Figure 36-1.
36.4 Pin Name List Table 36-3. TC pin list 36.5 Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Product Dependencies 36.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 36-4.
36.5.3 Interrupt The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires programming the IC before configuring the TC. 36.5.4 Fault Output The TC has the FAULT output internally connected to the fault input of PWM. Refer to Section 36.6.17 ”Fault Mode”, and to the product Pulse Width Modulation (PWM) implementation. 36.6 Functional Description 36.6.
Figure 36-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 36-3.
36.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 36-4. • • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
36.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.
36.6.9 Trigger Conditions TIOA RA RB Internal PDC trigger Transfer to System Memory RA RB RA RB T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK) ETRGEDG=3, LDRA=3, LDRB=0, ABETRG=0 TIOB TIOA RA Internal PDC trigger Transfer to System Memory RA RA RA RA T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK) In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
TIOA TIOB SYNC XC2 XC1 XC0 MTIOA MTIOB 1 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 ABETRG CLKI SWTRG If RA is not loaded or RB is Loaded Edge Detector ETRGEDG MCK Synchronous Edge Detection R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR Timer/Counter Channel BURST TCCLKS Compare RC = Register C COVFS INT
36.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB
36.6.11.1WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 36-8. RC Compare cannot be programmed to generate a trigger in this configuration.
36.6.11.2WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 36-10.
36.6.11.3WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-12.
36.6.11.4WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-14.
36.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 36.6.14 Quadrature Decoder Logic 36.6.14.
Figure 36-15.Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA0 QDEN PHEdges TIOA0 TIOB0 TIOB1 1 TIOB0 TIOB 1 XC0 XC0 PHA Speed/Position QDEN PHB IDX Timer/Counter Channel 0 TIOA Index 1 TIOB1 TIOB 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 36.6.14.
Figure 36-16.Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter FILTER PHedge 1 TIOA0 Direction and Edge Detection INVA 1 PHB Filter 1 DIR Filter 1 IDX TIOB0 INVB 1 1 IDX TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference.
Figure 36-17.
36.6.14.3Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the 2 quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime on TC_QISR register. The polarity of the direction flag status depends on the configuration written in TC_BMR register. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
to (MAXFILT+1) * tMCK ns. After being filtered there is no reason to have 2 edges closer than (MAXFILT+1) * tMCK ns under normal mode of operation. In the instance an anomaly occurs, a quadrature error is reported on QERR flag on TC_QISR register. Figure 36-19.
36.6.14.5Speed Measurement When SPEEDEN is set in TC_BMR register, the speed measure is enabled on channel 0. A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC value. ACPC field must be defined at 0x11 to toggle TIOA output.
36.6.17 Fault Mode At anytime, the TC_RCx registers can be used to perform a comparison on the respective current channel counter value (TC_CVx) with the value of TC_RCx register. The CPCSx flags can be set accordingly and an interrupt can be generated. This interrupt is processed but requires an unpredictable amount of time to be achieve the required action. It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 register and/or CPCS from TC_SR1 register.
36.7 Timer Counter (TC) User Interface Table 36-5.
36.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1], 0x40014080 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.
36.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
• LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.
36.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..
• CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event.
• ACPA: RA Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
• BCPC: RC Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 790
36.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..
36.7.5 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1], 0x40014090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
36.7.6 TC Register A Name: TC_RAx [x=0..
36.7.8 TC Register C Name: TC_RCx [x=0..2] Address: 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1], 0x4001409C (1)[2] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808 • RC: Register C RC contains the Register C value in real time.
36.7.9 TC Status Register Name: TC_SRx [x=0..
• ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high.
36.7.10 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1], 0x400140A4 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt.
36.7.11 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1], 0x400140A8 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt.
36.7.12 TC Interrupt Mask Register Name: TC_IMRx [x=0..2] Address: 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1], 0x400140AC (1)[2] Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled.
36.7.13 TC Block Control Register Name: TC_BCR Address: 0x400100C0 (0), 0x400140C0 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
36.7.14 TC Block Mode Register Name: TC_BMR Address: 0x400100C4 (0), 0x400140C4 (1) Access: Read-write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 25 21 20 19 FILTER 18 – 17 IDXPHB 16 SWAP 12 EDGPHA 11 QDTRANS 10 SPEEDEN 9 POSEN 8 QDEN 4 3 2 1 MAXFILT 15 INVIDX 14 INVB 13 INVA 7 – 6 – 5 TC2XC2S TC1XC1S 24 MAXFILT 0 TC0XC0S This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808.
• POSEN: POSition ENabled 0 = Disable position. 1 = Enables the position measure on channel 0 and 1. • SPEEDEN: SPEED ENabled 0 = Disabled. 1 = Enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding TRANSparent 0 = Full quadrature decoding logic is active (direction change detected). 1 = Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
36.7.15 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0x400100C8 (0), 0x400140C8 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0 = No effect. 1 = Enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0 = No effect.
36.7.16 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0x400100CC (0), 0x400140CC (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0 = No effect. 1 = Disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0 = No effect.
36.7.17 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0x400100D0 (0), 0x400140D0 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0 = The interrupt on IDX input is disabled. 1 = The interrupt on IDX input is enabled. • DIRCHG: DIRection CHanGe 0 = The interrupt on rotation direction change is disabled.
36.7.18 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0x400100D4 (0), 0x400140D4 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DIR 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0 = No Index input change since the last read of TC_QISR. 1 = The IDX input has changed since the last read of TC_QISR.
36.7.
36.7.20 TC Write Protect Mode Register Name: TC_WPMR Address: 0x400100E4 (0), 0x400140E4 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
37. High Speed MultiMedia Card Interface (HSMCI) 37.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
37.3 Block Diagram Figure 37-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt 37.4 Application Block Diagram Figure 37-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc.
37.5 Pin Name List Table 37-1. I/O Lines Description for 4-bit Configuration Pin Name(2) Pin Description Type(1) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2.
37.7 Bus Topology Figure 37-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 1011 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 37-4.
Figure 37-4. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 1011 9 1011 9 1011 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 37-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 37-5. Table 37-5.
MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 37-6. SD Card Bus Connections with One Slot Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command Register. The HSMCI_CMDR allows a command to be carried out.
The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (HSMCI_IER) allows using an interrupt method. Figure 37-7.
Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMedia Card specification). 37.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC).
Figure 37-8.
37.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart (Figure 37-9) shows how to write a single block with or without use of PDC facilities.
Figure 37-9.
Figure 37-10.
37.9 SD/SDIO Card Operation The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
37.10.1 Executing an ATA Polling Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA. 2. Read the ATA status register until DRQ is set. 3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 4. Read the ATA status register until DRQ && BSY are set to 0. 37.10.2 Executing an ATA Interrupt Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA with nIEN field set to zero to enable the command completion signal in the device. 2.
37.11 HSMCI Boot Operation Mode In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on register setting. As it is not possible to boot directly on SD-CARD, a preliminary boot code must be stored in internal Flash. 37.11.1 Boot Procedure, Processor Mode 1.
37.12.3 Write Access During a write access, the XFRDONE flag behaves as shown in Figure 37-12. Figure 37-12.XFRDONE During a Write Access CMD line HSMCI write CMD Card response CMDRDY flag The CMDRDY flag is released 8 tbit after the end of the card response. D0 is tied by the card D0 is released D0 1st Block Last Block 1st Block Last Block Data bus - D0 Not busy flag XFRDONE flag 37.
37.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 37-8.
37.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0x40000000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0 = No effect. 1 = Disables the Multi-Media Interface.
37.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0x40000004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 PDCMODE 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
• PDCMODE: PDC-oriented Mode 0 = Disables PDC transfer 1 = Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer has been completed.
37.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0x40000008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
37.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0x4000000C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851. • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
37.14.
37.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0x40000014 Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
• OPDCMD: Open Drain Command 0 (PUSHPULL) = Push pull command. 1 (OPENDRAIN) = Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved • TRDIR: Transfer Direction 0 (WRITE) = Write. 1 (READ) = Read.
37.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0x40000018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Command Register (HSMCI_CMDR).
37.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0x4000001C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
37.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0x40000020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
37.14.
37.14.
37.14.12HSMCI Status Register Name: HSMCI_SR Address: 0x40000040 Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent.
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block. The NOTBUSY flag allows to deal with these different states. 0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended.
• RCRCE: Response CRC Error 0 = No error. 1 = A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR. • RENDE: Response End Bit Error 0 = No error. 1 = The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR. • RTOE: Response Time-out Error 0 = No error. 1 = The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the HSMCI_CMDR. • DCRCE: Data CRC Error 0 = No error.
• OVRE: Overrun 0 = No error. 1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. When FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read. • UNRE: Underrun 0 = No error. 1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1. When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
37.14.
• DTOE: Data Time-out Error Interrupt Enable • CSTOE: Completion Signal Timeout Error Interrupt Enable • FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
37.14.
• DTOE: Data Time-out Error Interrupt Disable • CSTOE: Completion Signal Time out Error Interrupt Disable • FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
37.14.
• DTOE: Data Time-out Error Interrupt Mask • CSTOE: Completion Signal Time-out Error Interrupt Mask • FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
37.14.16HSMCI Configuration Register Name: HSMCI_CFG Address: 0x40000054 Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
37.14.17HSMCI Write Protect Mode Register Name: HSMCI_WPMR Address: 0x400000E4 Access: Read-write 31 30 29 28 27 WP_KEY (0x4D => “M”) 26 25 24 23 22 21 20 19 WP_KEY (0x43 => C”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII). 1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
37.14.
38. Pulse Width Modulation Controller (PWM) 38.1 Description The PWM macrocell controls 4 channels independently. Each channel controls two complementary square output waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks provided by the clock generator.
38.3 Two independent event lines which can send up to 4 triggers on ADC within a period One programmable Fault Input providing an asynchronous protection of outputs Stepper motor control (2 Channels) Block Diagram Figure 38-1.
38.5 Product Dependencies 38.5.1 I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 38-2.
Table 38-2. I/O Lines PWM PWML2 PA30 A PWM PWML2 PB13 A PWM PWML2 PC2 B PWM PWML3 PA15 C PWM PWML3 PC3 B PWM PWML3 PC22 B 38.5.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later.
38.6.1 PWM Clock Generator Figure 38-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR The PWM master clock (MCK) is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks.
38.6.2 PWM Channel 38.6.2.1 Channel Block Diagram Figure 38-3.
the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
Figure 38-4. Non Overlapped Center Aligned Waveforms No overlap OC0 OC1 Period Note: 1. See Figure 38-5 on page 861 for a detailed description of center aligned waveforms. When center aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period. When left aligned, the channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.
Figure 38-5.
Figure 38-6. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 38.6.2.4 Dead-Time Generator The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control switches safely.
Figure 38-7. Complementary Output Waveforms output waveform OCx CPOLx = 0 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx output waveform OCx CPOLx = 1 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 38.6.2.
By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the channel counter, as soon as the register is written. The value of the current output selection can be read in PWM_OS. While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are forced to user defined values. 38.6.2.6 Fault Protection 6 inputs provide fault protection which can force any of the PWM output pair to a programmable value.
When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this channel and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the “PWM Fault Protection Value Register” (PWM_FPV). The output forcing is made asynchronously to the channel counter.
(PWM_SCUC) is set to 1. The update of the duty-cycle values and the update period value is triggered automatically after an update period defined by the field UPR in the “PWM Sync Channels Update Period Register” (PWM_SCUP) (see “Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 867).
4. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write registers that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx). 5. Set UPDULOCK to 1 in PWM_SCUC. 6. The update of the registers will occur at the beginning of the next PWM period. At this moment the UPDULOCK bit is reset, go to Step 4.) for new values. Figure 38-10.
7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDULOCK is reset, go to Step 5. for new values. 8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update values is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2 register. 9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD). 10.
flag and the PDC transfer request with a comparison match (see Section 38.6.3 “PWM Comparison Units”), by the fields PTRM and PTRCS in the PWM_SCM register. ENDTX: this flag is set to 1 when a PDC transfer is completed TXBUFE: this flag is set to 1 when the PDC buffer is empty (no pending PDC transfers) UNRE: this flag is set to 1 when the update period defined by the UPR field has elapsed while the whole data has not been written by the PDC. It is reset to 0 when the PWM_ISR2 register is read.
Figure 38-12.Method 3 (UPDM=2 and PTRM=0) CCNT0 CDTYUPD UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x20 0x80 0xB0 0xA0 0x3 0x3 0x1 0x0 0x1 0x0 0x1 0x1 0x2 0x3 0x1 0x0 0x80 0x60 0x40 0x20 0x0 0x2 0xA0 transfer request WRDY Figure 38-13.
38.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 38.6.2.7 “Synchronous Channels”). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see Section 38.6.
The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not masked. These interrupts can be enabled by the “PWM Interrupt Enable Register 2” and disabled by the “PWM Interrupt Disable Register 2” . The comparison match interrupt and the comparison update interrupt are reset by reading the “PWM Interrupt Status Register 2” . Figure 38-15.
38.6.4 PWM Event Lines The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in particular for ADC (Analog-to-Digital Converter)). A pulse (one cycle of the master clock (MCK)) is generated on an event line, when at least one of the selected comparisons is matching. The comparisons can be selected or unselected independently by the CSEL bits in the “PWM Event Line x Register” (PWM_ELMRx for the Event Line x). Figure 38-16.
Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing WRDYE, ENDTXE, TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register) Enable of the PWM channels (writing CHIDx in the PWM_ENA register) 38.6.5.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the “PWM Channel Period Register” (PWM_CPRDx) and the “PWM Channel Duty Cycle Register” (PWM_CDTYx) can help the user in choosing.
Note: If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and UPDM=1 or 2 in PWM_SCM register): registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-times values until the bit UPDULOCK is written at “1” (in PWM_SCUC register) and the end of the current PWM period, then update the values for the next period.
38.6.5.4 Changing the Synchronous Channels Update Period It is possible to change the update period of synchronous channels while they are enabled. (See “Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 867 and “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on page 868.
38.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see Section 38.6.3 “PWM Comparison Units”).
38.6.5.7 Write Protect Registers To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-protected by writing the field WPCMD in the “PWM Write Protect Control Register” on page 911 (PWM_WPCR).
38.7 Pulse Width Modulation Controller (PWM) Controller User Interface Table 38-6.
Table 38-6.
Table 38-6.
38.7.1 PWM Clock Register Name: PWM_CLK Address: 0x40020000 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA This register can only be written if the bits WPSWS0 and WPHWS0 are cleared in “PWM Write Protect Status Register” on page 913.
38.7.2 PWM Enable Register Name: PWM_ENA Address: 0x40020004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
38.7.3 PWM Disable Register Name: PWM_DIS Address: 0x40020008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if the bits WPSWS1 and WPHWS1 are cleared in “PWM Write Protect Status Register” on page 913. • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
38.7.4 PWM Status Register Name: PWM_SR Address: 0x4002000C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
38.7.
38.7.
38.7.
38.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Address: 0x4002001C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x 0 = No new counter event has occurred since the last read of the PWM_ISR1 register.
38.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Address: 0x40020020 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 23 22 PTRCS 21 20 PTRM 19 – 18 – 17 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 24 – 16 UPDM This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page 913. • SYNCx: Synchronous Channel x 0 = Channel x is not a synchronous channel.
38.7.
38.7.11 PWM Sync Channels Update Period Register Name: PWM_SCUP Address: 0x4002002C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR • UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” on page 890).
38.7.12 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Address: 0x40020030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.
38.7.
38.7.
38.7.
38.7.16 PWM Interrupt Status Register 2 Name: PWM_ISR2 Address: 0x40020040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update 0 = New duty-cycle and dead-time values for the synchronous channels cannot be written.
38.7.17 PWM Output Override Value Register Name: PWM_OOV Address: 0x40020044 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 • OOVHx: Output Override Value for PWMH output of the channel x 0 = Override value is 0 for PWMH output of channel x. 1 = Override value is 1 for PWMH output of channel x.
38.7.18 PWM Output Selection Register Name: PWM_OS Address: 0x40020048 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSH3 2 OSH2 1 OSH1 0 OSH0 • OSHx: Output Selection for PWMH output of the channel x 0 = Dead-time generator output DTOHx selected as PWMH output of channel x. 1 = Output override value OOVHx selected as PWMH output of channel x.
38.7.19 PWM Output Selection Set Register Name: PWM_OSS Address: 0x4002004C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 • OSSHx: Output Selection Set for PWMH output of the channel x 0 = No effect. 1 = Output override value OOVHx selected as PWMH output of channel x.
38.7.20 PWM Output Selection Clear Register Name: PWM_OSC Address: 0x40020050 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 • OSCHx: Output Selection Clear for PWMH output of the channel x 0 = No effect. 1 = Dead-time generator output DTOHx selected as PWMH output of channel x.
38.7.21 PWM Output Selection Set Update Register Name: PWM_OSSUPD Address: 0x40020054 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 • OSSUPHx: Output Selection Set for PWMH output of the channel x 0 = No effect.
38.7.22 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Address: 0x40020058 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 • OSCUPHx: Output Selection Clear for PWMH output of the channel x 0 = No effect.
38.7.23 PWM Fault Mode Register Name: PWM_FMR Address: 0x4002005C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 913.
38.7.24 PWM Fault Status Register Name: PWM_FSR Address: 0x40020060 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV • FIV: Fault Input Value (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The current sampled value of the fault input y is 0 (after filtering if enabled). 1 = The current sampled value of the fault input y is 1 (after filtering if enabled).
38.7.25 PWM Fault Clear Register Name: PWM_FCR Address: 0x40020064 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR • FCLR: Fault Clear (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = No effect.
38.7.26 PWM Fault Protection Value Register Name: PWM_FPV Address: 0x40020068 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 913.
38.7.27 PWM Fault Protection Enable Register Name: PWM_FPE Address: 0x4002006C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 913. Only the first 6 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant.
38.7.28 PWM Event Line x Register Name: PWM_ELMRx Address: 0x4002007C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 • CSELy: Comparison y Selection 0 = A pulse is not generated on the event line x when the comparison y matches. 1 = A pulse is generated on the event line x when the comparison y match.
38.7.29 PWM Stepper Motor Mode Register Name: PWM_SMMR Address: 0x400200B0 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 GCEN1 0 GCEN0 • GCENx: Gray Count ENable 0 = Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1 = enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.
38.7.30 PWM Write Protect Control Register Name: PWM_WPCR Address: 0x400200E4 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 0 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 WPCMD • WPCMD: Write Protect Command This command is performed only if the WPKEY value is correct. 0 = Disable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
• Register group 4: – “PWM Channel Dead Time Register” on page 925 – “PWM Channel Dead Time Update Register” on page 926 • Register group 5: – “PWM Fault Mode Register” on page 904 – “PWM Fault Protection Value Register” on page 907 SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 912
38.7.31 PWM Write Protect Status Register Name: PWM_WPSR Address: 0x400200E8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 • WPSWSx: Write Protect SW Status 0 = The Write Protect SW x of the register group x is disabled. 1 = The Write Protect SW x of the register group x is enabled.
38.7.32 PWM Comparison x Value Register Name: PWM_CMPVx Address: 0x40020130 [0], 0x40020140 [1], 0x40020150 [2], 0x40020160 [3], 0x40020170 [4], 0x40020180 [5], 0x40020190 [6], 0x400201A0 [7] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVM 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant.
38.7.33 PWM Comparison x Value Update Register Name: PWM_CMPVUPDx Address: 0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5], 0x40020194 [6], 0x400201A4 [7] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVMUPD 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
38.7.34 PWM Comparison x Mode Register Name: PWM_CMPMx Address: 0x40020138 [0], 0x40020148 [1], 0x40020158 [2], 0x40020168 [3], 0x40020178 [4], 0x40020188 [5], 0x40020198 [6], 0x400201A8 [7] Access: Read-write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 21 20 19 18 CUPRCNT 15 14 13 6 24 – 17 16 9 8 1 – 0 CEN CUPR 12 11 10 CPRCNT 7 25 – CPR 5 4 CTR 3 – 2 – • CEN: Comparison x Enable 0 = The comparison x is disabled and can not match.
38.7.35 PWM Comparison x Mode Update Register Name: PWM_CMPMUPDx Address: 0x4002013C [0], 0x4002014C [1], 0x4002015C [2], 0x4002016C [3], 0x4002017C [4], 0x4002018C [5], 0x4002019C [6], 0x400201AC [7] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 – 11 7 6 5 4 3 – CTRUPD 25 – 24 – 17 16 9 8 1 – 0 CENUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values.
38.7.36 PWM Channel Mode Register Name: PWM_CMRx [x=0..3] Address: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3] Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DTLI 17 DTHI 16 DTE 15 – 14 – 13 – 12 – 11 – 10 CES 9 CPOL 8 CALG 7 – 6 – 5 – 4 – 3 2 1 0 CPRE This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page 913.
• CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in the “PWM Interrupt Status Register 1” on page 889). CALG = 0 (Left Alignment): 0/1 = The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0 = The channel counter event occurs at the end of the PWM period. 1 = The channel counter event occurs at the end of the PWM period and at half the PWM period.
38.7.37 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..3] Address: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. • CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
38.7.38 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..3] Address: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3] Access: Write-only. 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle.
38.7.39 PWM Channel Period Register Name: PWM_CPRDx [x=0..3] Address: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page 913. Only the first 16 bits (channel counter size) are significant.
38.7.40 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..3] Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page 913. This register acts as a double buffer for the CPRD value.
38.7.41 PWM Channel Counter Register Name: PWM_CCNTx [x=0..3] Address: 0x40020214 [0], 0x40020234 [1], 0x40020254 [2], 0x40020274 [3] Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. • CNT: Channel Counter Register Channel counter value.
38.7.42 PWM Channel Dead Time Register Name: PWM_DTx [x=0..3] Address: 0x40020218 [0], 0x40020238 [1], 0x40020258 [2], 0x40020278 [3] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 913. Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant.
38.7.43 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..3] Address: 0x4002021C [0], 0x4002023C [1], 0x4002025C [2], 0x4002027C [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 913. This register acts as a double buffer for the DTH and DTL values.
39. USB Device Port (UDP) 39.1 Description The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
39.3 Block Diagram Figure 39-1. Block Diagram Atmel Bridge MCK USB Device APB to MCU Bus txoen U s e r I n t e r f a c e UDPCK udp_int W r a p p e r Dual Port RAM FIFO W r a p p e r eopn Serial Interface Engine 12 MHz txd rxdm Embedded USB Transceiver DDP DDM rxd SIE rxdp Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers.
39.4 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off.
39.5 Typical Connection Figure 39-2. Board Schematic to Interface Device Peripheral PIO 5V Bus Monitoring 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 39.5.1 USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows: the application detects all device states as defined in chapter 9 of the USB specification; VBUS monitoring to reduce power consumption the host is disconnected for line termination. 39.5.
39.6 Functional Description 39.6.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 39-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
39.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 39-5.
Figure 39-4. Control Read and Write Sequences Setup Stage Control Read Setup TX Data Stage Data OUT TX Setup Stage Control Write No Data Control Setup TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Data IN TX Status IN TX Status Stage Status OUT TX Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID.
Figure 39-5. Setup Transaction Followed by a Data OUT Transaction Setup Received USB Bus Packets Setup PID Data Setup Setup Handled by Firmware ACK PID RXSETUP Flag Data OUT PID Data OUT Data Out Received NAK PID Data OUT ACK PID Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content Data OUT PID XX Data Setup XX Data OUT 39.6.2.
Figure 39-6.
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3.
39.6.2.3 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with pingpong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint.
Figure 39-10.
Figure 39-11.
Figure 39-12.Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 39-13.Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID Set by Firmware FORCESTALL Interrupt Pending STALLSENT Cleared by Firmware Set by USB Device 39.6.2.
Set TXPKTRDY and read it back until actually read at 1. Clear TXPKTRDY so that no packet is ready to be sent. Reset the endpoint to clear the FIFO (pointers). (See, Section 39.7.9 ”UDP Reset Endpoint Register”.) 39.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 39-14.
39.6.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors. 39.6.3.2 Entering Attached State To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 39.6.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pull-up shall not be removed).
39.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 39-6.
39.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0x40034000 Access: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
39.7.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0x40034004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 RMWUPE 3 RSMINPR 2 ESR 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state.
39.7.3 UDP Function Address Register Name: UDP_FADDR Address: 0x40034008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
39.7.
39.7.
39.7.
• WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wake-up Interrupt is disabled. 1 = USB Bus Wake-up Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.
39.7.
• RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised.
39.7.8 UDP Interrupt Clear Register Name: UDP_ICR Address: 0x40034020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 EXTRSM 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.
39.7.
39.7.10 UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints) Name: UDP_CSRx [x = 0..
/// Clears the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to clear to 0.
• RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
• EPTYPE[2:0]: Endpoint Type Read-Write Value Name Description 000 CTRL Control 001 ISO_OUT Isochronous OUT 101 ISO_IN Isochronous IN 010 BULK_OUT Bulk OUT 110 BULK_IN Bulk IN 011 INT_OUT Interrupt OUT 111 INT_IN Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
39.7.11 UDP Endpoint Control and Status Register (Isochronous Endpoints) Name: UDP_CSRx [x = 0..
• RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
• EPTYPE[2:0]: Endpoint Type Read-Write Value Name Description 000 CTRL Control 001 ISO_OUT Isochronous OUT 101 ISO_IN Isochronous IN 010 BULK_OUT Bulk OUT 110 BULK_IN Bulk IN 011 INT_OUT Interrupt OUT 111 INT_IN Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
39.7.12 UDP FIFO Data Register Name: UDP_FDRx [x = 0..7] Address: 0x40034050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host).
39.7.13 UDP Transceiver Control Register Name: UDP_TXVC Address: 0x40034074 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
40. Analog Comparator Controller (ACC) 40.1 Description The Analog Comparator Controller (ACC) configures the Analog Comparator and generates an interrupt according to the user settings. The analog comparator embeds 8 to 1 multiplexers on both inputs. The Analog Comparator compares two voltages and the result of this comparison gives a compare output. The user can select a high-speed or low-power option. Additionally, the hysteresis level, edge detection and polarity are configurable.
40.4 Pin Name List Table 40-1. ACC Pin List 40.5 Pin Name Description Type AD0..AD7 Analog Inputs Input TS On-Chip Temperature Sensor Input ADVREF ADC Voltage Reference. Input DAC0, DAC1 On-Chip DAC Outputs Input FAULT Drives internal fault input of PWM Output Product Dependencies 40.5.1 I/O Lines The analog input pins (AD0-AD7 and DAC0-1) are multiplexed with PIO lines.
40.6 Functional Description 40.6.1 ACC Description The Analog Comparator Controller mainly controls the analog comparator settings. There is also post processing of the analog comparator output. The output of the analog comparator is masked for the time the output may be invalid. This situation is encountered as soon as the analog comparator settings are modified. A comparison flag is triggered by an event on the output of the analog comparator and an interrupt can be generated accordingly.
40.7 Analog Comparator Controller (ACC) User Interface Table 40-3.
40.7.1 ACC Control Register Name: ACC_CR Address: 0x40040000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: SoftWare ReSeT 0 = No effect. 1 = Resets the module.
40.7.2 ACC Mode Register Name: ACC_MR Address: 0x40040004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 FE 13 SELFS 12 INV 11 – 10 9 8 ACEN 7 – 6 5 SELPLUS 4 3 – 2 1 SELMINUS 0 EDGETYP This register can only be written if the WPEN bit is cleared in the ACC Write Protect Mode Register. • SELMINUS: SELection for MINUS comparator input 0..
• ACEN: Analog Comparator ENable 0 (DIS) = Analog Comparator Disabled. 1 (EN) = Analog Comparator Enabled. • EDGETYP: EDGE TYPe Value Name Description 0 RISING only rising edge of comparator output 1 FALLING falling edge of comparator output 2 ANY any edge of comparator output • INV: INVert comparator output 0 (DIS) = Analog Comparator output is directly processed. 1 (EN) = Analog Comparator output is inverted prior to being processed.
40.7.3 ACC Interrupt Enable Register Name: ACC_IER Address: 0x40040024 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE • CE: Comparison Edge 0 = No effect. 1 = Enables the interruption when the selected edge (defined by EDGETYP) occurs.
40.7.4 ACC Interrupt Disable Register Name: ACC_IDR Address: 0x40040028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE • CE: Comparison Edge 0 = No effect. 1 = Disables the interruption when the selected edge (defined by EDGETYP) occurs.
40.7.5 ACC Interrupt Mask Register Name: ACC_IMR Address: 0x4004002C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE • CE: Comparison Edge 0 = The interruption is disabled. 1 = The interruption is enabled.
40.7.6 ACC Interrupt Status Register Name: ACC_ISR Address: 0x40040030 Access: Read-only 31 MASK 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 SCO 0 CE • CE: Comparison Edge 0 = No edge occurred (defined by EDGETYP) on analog comparator output since the last read of ACC_ISR register.
40.7.7 ACC Analog Control Register Name: ACC_ACR Address: 0x40040094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 ISEL HYST This register can only be written if the WPEN bit is cleared in ACC Write Protect Mode Register. • ISEL: Current SELection Refer to the product Electrical Characteristics. 0 (LOPW) = Low power option. 1 (HISP) = High speed option.
40.7.8 ACC Write Protect Mode Register Name: ACC_WPMR Address: 0x400400E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414343 (“ACC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414343 (“ACC” in ASCII).
40.7.9 ACC Write Protect Status Register Name: ACC_WPSR Address: 0x400400E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WPROTERR • WPROTERR: Write PROTection ERRor 0 = No Write Protect Violation has occurred since the last read of the ACC_WPSR register.
41. Analog-to-Digital Converter (ADC) 41.1 Description The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block Diagram: Figure 41-1. It also integrates a 16-to-1 analog multiplexer, making possible the analog-to-digital conversions of 16 analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF.
41.3 Block Diagram Figure 41-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC 12-Bit Controller Trigger Selection ADTRG Control Logic ADC cell ADC Interrupt Interrupt Controller AHB PDC ADVREF AD0 Peripheral Bridge PIO Analog Inputs AD1 IN+ IN- OFFSET S/H PGA ADn Cyclic Pipeline 12-bit Analog-to-Digital Converter User Interface APB CHx GND Note: 41.4 DMA is sometimes referenced as PDC (Peripheral DMA Controller). Signal Description Table 41-1.
41.5.3 Analog Inputs The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND. 41.5.4 Temperature Sensor The temperature sensor is internally connected to channel 15 of the ADC.
41.5.8 Fault Output The ADC Controller has the FAULT output connected to the FAULT input of PWM. Please refer to Section 41.6.13 ”Fault Output” and implementation of the PWM in the product. 41.5.9 Conversion Performances For performance and electrical characteristics of the ADC, see the product DC Characteristics section. 41.6 Functional Description 41.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions.
Figure 41-3. Sequence of ADC conversions when Tracking time < Conversion time Read the ADC_LCDR ADCClock Trigger event (Hard or Soft) ADC_ON Commands from controller to analog cell ADC_Start ADC_SEL CH0 CH1 LCDR CH3 CH2 CH0 CH1 CH2 DRDY Start Up Time & Tracking of CH0 Transfer Period Conversion of CH0 & Tracking of CH1 Transfer Period Conversion of CH1 & Tracking of CH2 Transfer Period Conversion of CH2 & Tracking of CH3 41.6.
Figure 41-4. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) DRDY (ADC_SR) If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER). Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
Figure 41-5.
41.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register (ADC_MR).
If all ADC channels (i.e. 16) are used on an application board, there is no restriction of usage of the user sequence. But as soon as some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective indexes of these channels cannot be used in the user sequence fields (ADC_SEQR1, ADC_SEQR2 bitfields). For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields USCH1 up to USCH16 must not contain the value 4.
Table 41-4. Input Pins and Channel Number in Single Ended Mode (Continued) Input Pins Channel Number AD10 CH10 AD11 CH11 AD12 CH12 AD13 CH13 AD14 CH14 AD15 CH15 Table 41-5. Input Pins and Channel Number In Differential Mode Input Pins Channel Number AD0-AD1 CH0 AD2-AD3 CH2 AD4-AD5 CH4 AD6-AD7 CH6 AD8-AD9 CH8 AD10-AD11 CH10 AD12-AD13 CH12 AD14-AD15 CH14 41.6.9 Input Gain and Offset The ADC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset.
Figure 41-6. Analog Full Scale Ranges in Single Ended/Differential Applications Versus Gain and Offset single ended se0fd1=0 fully differential se0fd1=1 vrefin VIN+ VIN+ same as gain=1 gain=0.
When the gain, offset or differential input parameters of the analog cell change between two channels, the analog cell may need a specific settling time before starting the tracking phase. In that case, the controller automatically waits during the settling time defined in the “ADC Mode Register”. Obviously, if the ANACH option is not set, this time is unused. Warning: No input buffer amplifier to isolate the source is included in the ADC.
41.6.14 Write Protected Registers To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
41.7 Analog-to-Digital Converter (ADC) User Interface Any offset not listed in Table 41-8 must be considered as “reserved”. Table 41-8.
41.7.1 ADC Control Register Name: ADC_CR Address: 0x40038000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 AUTOCAL 2 – 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. • AUTOCAL: Automatic Calibration of ADC 0 = No effect.
41.7.2 ADC Mode Register Name: ADC_MR Address: 0x40038004 Access: Read-write 31 USEQ 30 – 29 23 ANACH 22 – 21 15 14 13 28 27 26 TRANSFER 25 24 17 16 TRACKTIM 20 19 18 SETTLING STARTUP 12 11 10 9 8 3 2 TRGSEL 1 0 TRGEN PRESCAL 7 FREERUN 6 FWUP 5 SLEEP 4 LOWRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015. • TRGEN: Trigger Enable Value Name Description 0 DIS Hardware triggers are disabled.
• SLEEP: Sleep Mode Value Name 0 NORMAL 1 SLEEP Description Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions Sleep Mode: The wake-up time can be modified by programming FWUP bit • FWUP: Fast Wake Up Value Name Description 0 OFF If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions 1 ON If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF • FREERUN: Free R
• SETTLING: Analog Settling Time Value Name Description 0 AST3 3 periods of ADCClock 1 AST5 5 periods of ADCClock 2 AST9 9 periods of ADCClock 3 AST17 17 periods of ADCClock • ANACH: Analog Change Value Name Description 0 NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels 1 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * ADCClock periods.
41.7.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0x40038008 Access: Read-write 31 – 30 29 USCH8 28 27 – 26 25 USCH7 24 23 – 22 21 USCH6 20 19 – 18 17 USCH5 16 15 – 14 13 USCH4 12 11 – 10 9 USCH3 8 7 – 6 5 USCH2 4 3 – 2 1 USCH1 0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
41.7.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0x4003800C Access: Read-write 31 – 30 29 USCH16 28 27 – 26 25 USCH15 24 23 – 22 21 USCH14 20 19 – 18 17 USCH13 16 15 – 14 13 USCH12 12 11 – 10 9 USCH11 8 7 – 6 5 USCH10 4 3 – 2 1 USCH9 0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
41.7.5 ADC Channel Enable Register Name: ADC_CHER Address: 0x40038010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015. • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
41.7.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0x40038014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015. • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
41.7.7 ADC Channel Status Register Name: ADC_CHSR Address: 0x40038018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled. 41.7.
41.7.
41.7.
41.7.
41.7.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0x40038030 Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished.
41.7.13 ADC Overrun Status Register Name: ADC_OVER Address: 0x4003803C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 OVRE15 14 OVRE14 13 OVRE13 12 OVRE12 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
41.7.14 ADC Extended Mode Register Name: ADC_EMR Address: 0x40038040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 CMPALL 8 – 7 6 5 4 3 – 2 – 1 0 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
41.7.15 ADC Compare Window Register Name: ADC_CWR Address: 0x40038044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015. • LOWTHRES: Low Threshold Low threshold associated to compare settings of the ADC_EMR register.
41.7.16 ADC Channel Gain Register Name: ADC_CGR Address: 0x40038048 Access: Read-write 31 30 29 GAIN15 23 22 21 GAIN11 15 27 14 20 13 19 6 12 5 25 18 11 17 4 10 3 9 8 GAIN4 2 GAIN1 16 GAIN8 GAIN5 GAIN2 24 GAIN12 GAIN9 GAIN6 GAIN3 26 GAIN13 GAIN10 GAIN7 7 28 GAIN14 1 0 GAIN0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
41.7.17 ADC Channel Offset Register Name: ADC_COR Address: 0x4003804C Access: Read-write 31 DIFF15 30 DIFF14 29 DIFF13 28 DIFF12 27 DIFF11 26 DIFF10 25 DIFF9 24 DIFF8 23 DIFF7 22 DIFF6 21 DIFF5 20 DIFF4 19 DIFF3 18 DIFF2 17 DIFF1 16 DIFF0 15 OFF15 14 OFF14 13 OFF13 12 OFF12 11 OFF11 10 OFF10 9 OFF9 8 OFF8 7 OFF7 6 OFF6 5 OFF5 4 OFF4 3 OFF3 2 OFF2 1 OFF1 0 OFF0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
41.7.18 ADC Channel Data Register Name: ADC_CDRx [x=0..15] Address: 0x40038050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
41.7.19 ADC Analog Control Register Name: ADC_ACR Address: 0x40038094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 – 6 – 5 – 4 TSON 3 – 2 – 1 – 8 IBCTL 0 – This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015. • TSON: Temperature Sensor On 0 = temperature sensor is off. 1 = temperature sensor is on.
41.7.20 ADC Write Protect Mode Register Name: ADC_WPMR Address: 0x400380E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
41.7.21 ADC Write Protect Status Register Name: ADC_WPSR Address: 0x400380E8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register.
42. Digital-to-Analog Converter Controller (DACC) 42.1 Description The Digital-to-Analog Converter Controller (DACC) offers up to 2 analog outputs, making it possible for the digital-toanalog conversion to drive up to 2 independent analog lines. The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels. External triggers or free running mode are configurable. The DACC integrates a Sleep Mode and connects with a PDC channel.
42.3 Block Diagram Figure 42-1. Digital-to-Analog Converter Controller Block Diagram DAC Controller Trigger Selection DATRG Control Logic Interrupt Controller Analog Cell DAC Core PDC 42.4 Sample & Hold Sample & Hold AHB DAC0 DAC1 User Interface Peripheral Bridge APB Signal Description Table 42-1.
42.5 Product Dependencies 42.5.1 Power Management The programmer must first enable the DAC Controller Clock in the Power Management Controller (PMC) before using the DACC. The DACC becomes active as soon as a conversion is requested and at least one channel is enabled. The DACC is automatically deactivated when no channels are enabled. For power saving options see Section 42.6.6 ”Sleep Mode”. 42.5.
42.6 Functional Description 42.6.1 Digital-to-Analog Conversion The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is named DACC Clock. Once a conversion starts the DACC takes 25 clock periods to provide the analog result on the selected analog output. 42.6.2 Conversion Results When a conversion is completed, the resulting analog value is available at the selected DACC channel output and the EOC bit in the DACC Interrupt Status Register, is set.
42.6.6 Sleep Mode The DACC Sleep Mode maximizes power saving by automatically deactivating the DACC when it is not being used for conversions. When a start conversion request occurs, the DACC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the selected channel. When all conversion requests are complete, the DACC is deactivated until the next request for conversion.
42.6.8 Write Protection Registers In order to provide security to the DACC, a write protection system has been implemented. The write protection mode prevents the writing of certain registers. When this mode is enabled and one of the protected registers is written, an error is generated in the DACC Write Protect Status Register and the register write request is canceled.
42.7 Digital-to-Analog Converter (DACC) User Interface Table 42-3.
42.7.1 DACC Control Register Name: DACC_CR Address: 0x4003C000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the DACC simulating a hardware reset.
42.7.2 DACC Mode Register Name: DACC_MR Address: 0x4003C004 Access: Read-write 31 – 30 – 29 23 – 22 – 21 MAXS 20 TAG 15 14 13 12 28 27 26 25 24 19 – 18 – 17 11 10 9 8 3 2 TRGSEL 1 0 TRGEN STARTUP 16 USER_SEL REFRESH 7 – 6 FASTWKUP 5 SLEEP 4 WORD This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • TRGEN: Trigger Enable Value Name Description 0 DIS External trigger mode disabled. DACC in free running mode.
• SLEEP: Sleep Mode SLEEP Selected Mode 0 Normal Mode 1 Sleep Mode 0 = Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. After reset, the DAC is in normal mode but with the voltage reference and the DAC core off. For the first conversion, a startup time must be defined in the STARTUP field. Note that in this mode, STARTUP time is only required once, at start up. 1 = Sleep Mode: The DAC Core and reference voltage circuitry are OFF between conversions.
• STARTUP: Startup Time Selection Value Name 0 0 1 Description Value Name Description 0 periods of DACClock 32 2048 2048 periods of DACClock 8 8 periods of DACClock 33 2112 2112 periods of DACClock 2 16 16 periods of DACClock 34 2176 2176 periods of DACClock 3 24 24 periods of DACClock 35 2240 2240 periods of DACClock 4 64 64 periods of DACClock 36 2304 2304 periods of DACClock 5 80 80 periods of DACClock 37 2368 2368 periods of DACClock 6 96 96 periods of DACCloc
42.7.3 DACC Channel Enable Register Name: DACC_CHER Address: 0x4003C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
42.7.4 DACC Channel Disable Register Name: DACC_CHDR Address: 0x4003C014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
42.7.5 DACC Channel Status Register Name: DACC_CHSR Address: 0x4003C018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
42.7.6 DACC Conversion Data Register Name: DACC_CDR Address: 0x4003C020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Convert When the WORD bit in DACC_MR register is cleared, only DATA[15:0] is used else DATA[31:0] is used to write 2 data to be converted.
42.7.
42.7.8 DACC Interrupt Disable Register Name: DACC_IDR Address: 0x4003C028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable.
42.7.
42.7.10 DACC Interrupt Status Register Name: DACC_ISR Address: 0x4003C030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY • TXRDY: Transmit Ready Interrupt Flag 0 = DACC is not ready to accept new conversion requests. 1 = DACC is ready to accept new conversion requests.
42.7.11 DACC Analog Current Register Name: DACC_ACR Address: 0x4003C094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 IBCTLDACCORE 7 – 6 – 5 – 4 – 3 2 1 IBCTLCH1 0 IBCTLCH0 This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • IBCTLCHx: Analog Output Current Control Allows to adapt the slew rate of the analog output.
42.7.12 DACC Write Protect Mode Register Name: DACC_WPMR Address: 0x4003C0E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
42.7.13 DACC Write Protect Status Register Name: DACC_WPSR Address: 0x4003C0E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 WPROTADDR 10 9 8 7 – 6 – 5 – 4 – 2 – 1 – 0 WPROTERR 3 – • WPROTADDR: Write protection error address Indicates the address of the register write request which generated the error. • WPROTERR: Write protection error Indicates a write protection error.
43. SAM4S Electrical Characteristics 43.1 Absolute Maximum Ratings Table 43-1. Absolute Maximum Ratings* *NOTICE: Storage Temperature..............................-60°C to + 150°C Voltage on Input Pins with Respect to Ground..............................-0.3V to + 4.0V Maximum Operating Voltage (VDDCORE)...............................................................1.32V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
43.2 DC Characteristics The following characteristics are applicable to the operating temperature range: T= -40°C to 105°C, unless otherwise specified. Table 43-2.
Table 43-2. DC Characteristics (Continued) Symbol Parameter IIH Input High RPULLUP Pull-up Resistor RPULLDO Pull-down Resistor WN RODT On-die Series Termination Resistor Conditions Min Typ Max Pull-down OFF -1 — 1 Pull-down ON 10 — 50 70 100 130 kΩ 70 100 130 kΩ PA0–PA31, PB0–PB14, PC0–PC31 NRST PA0–PA31, PB0–PB14, PC0–PC31 NRST PA4–PA31, PB0–PB9, PB12–PB14, PC0–PC31 PA0-PA3 — 36 Units μA Ω 18 Random 144-bit Read @ 25°C : Maximum read frequency onto VDDCORE = 1.
Table 43-3. 1.2V Voltage Regulator Characteristics Symbol Parameter Conditions Min Typ Max Units VVDDIN DC Input Voltage Range (4) (5) 1.6 3.3 3.6 V VVDDOUT DC Output Voltage — V VACCURACY Output Voltage Accuracy ILoad = 0.8 mA to 80 mA(after trimming) 3 % ILOAD Maximum DC Output Current VVDDIN > 1.8V Normal Mode 1.2 — Standby Mode VVDDIN ≤ 1.8V 0 -3 — — 80 40 mA Maximum Peak Current during Startup See Note(3). — — 400 mA DDROPOUT Dropout Voltage VVDDIN = 1.
Table 43-4. Core Power Supply Brownout Detector Characteristics Symbol Parameter VTH- Supply Falling Threshold(1) VHYST VTH+ Min Typ Max Units 0.98 1.0 1.04 V Hysteresis — — 110 mV Supply Rising Threshold 0.8 1.0 1.
Table 43-6. Threshold Selection Digital Code Threshold Min (V) Threshold Typ (V) Threshold Max (V) 0000 1.56 1.6 1.64 0001 1.68 1.72 1.76 0010 1.79 1.84 1.89 0011 1.91 1.96 2.01 0100 2.03 2.08 2.13 0101 2.15 2.2 2.23 0110 2.26 2.32 2.38 0111 2.38 2.44 2.50 1000 2.50 2.56 2.62 1001 2.61 2.68 2.75 1010 2.73 2.8 2.87 1011 2.85 2.92 2.99 1100 2.96 3.04 3.12 1101 3.08 3.16 3.24 1110 3.20 3.28 3.36 1111 3.32 3.4 3.49 Figure 43-2.
Table 43-7. Zero-Power-on Reset Characteristics Symbol Parameter Conditions Min Typ Max Units Vth+ Threshold Voltage Rising At startup 1.45 1.53 1.59 V Vth- Threshold Voltage Falling 1.35 1.45 1.55 V Tres Reset Time-out Period 100 340 580 μs Figure 43-3.
43.3 Power Consumption Power consumption of the device according to the different Low Power mode capabilities (backup, wait, sleep) and active mode. Power consumption on power supply in different modes: backup, wait, sleep and active. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. All power consumption values are based on characterization.
Table 43-9. Power Consumption for Backup Mode (SAM4SD32/SD16/SA16 rev A) Backup Total Consumption Typical value @25°C Maximum Value @85°C Maximum Value @105°C Unit Unit Conditions (AMP1) Configuration A (AMP1) Configuration B (AMP1) Configuration A (AMP1) Configuration A VDDIO = 3.6V 2.1 2.0 15.2 25.9 VDDIO = 3.3V 1.8 1.8 14.6 NA VDDIO = 3.0V 1.7 1.6 13.4 NA VDDIO = 2.5V 1.3 1.3 11.8 NA VDDIO = 1.8V 0.9 0.9 10.8 NA µA 43.3.
Figure 43-6. SAM4S16/S8 Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from Table 43-10) Table 43-10. SAM4S16/S8 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with PLLA Sleep Mode Consumption Typical value @25°C VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit Core Clock/MCK (MHz) 120 8.1 9.6 mA 100 7.1 8.1 mA 84 6.0 6.8 mA 64 4.7 5.2 mA 48 3.5 3.9 mA 32 2.4 2.6 mA 24 1.8 2.
Table 43-11. SAM4S16/S8 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with Fast RC Sleep Mode Consumption Typical value @25°C VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit Core Clock/MCK (MHz) 12 1.1 1.5 mA 8 0.7 1.2 mA 4 0.4 0.7 mA 2 0.3 0.7 mA 1 0.2 0.5 mA 0.5 0.2 0.
Figure 43-7. SAM4SD32/SD16/SA16 Typical Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from Table 43-12) Table 43-12. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with PLLA Sleep Mode Consumption Typical value @25°C Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 120 8.4 10.6 mA 100 7.1 8.9 mA 84 6.0 7.5 mA 64 4.6 5.8 mA 48 3.5 4.4 mA 32 2.4 3.1 mA 24 1.8 2.
Table 43-13. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with FAST RC Sleep Mode Consumption Typical value @25°C Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 12 1.1 1.8 mA 8 0.8 1.2 mA 4 0.4 0.7 mA 2 0.3 0.7 mA 1 0.2 0.5 mA 0.5 0.2 0.5 mA 43.3.2.2 Wait Mode Figure 43-8. Measurement Setup for Wait Mode AMP2 3.3V VDDIO VDDIN AMP1 Voltage Regulator VDDOUT VDDCORE VDDPLL VDDIO = VDDIN = 3.
Table 43-14. SAM4S16/S8 Typical Current Consumption in Wait Mode Wait Mode Consumption Typical value @25°C Conditions Maximum Value @85°C Maximum Value @105°C VDDOUT Consumption (AMP1) Total Consumption (AMP2) Total Consumption (AMP2) Total Consumption (AMP2 Unit 20.5 32.7 484 929 μA 20.5 27.8 479 918 μA See Figure 43-8 on page 1051 There is no activity on the I/Os of the device. With the Flash in standby mode See Figure 43-8 on page 1051 There is no activity on the I/Os of the device.
Figure 43-9. Active Mode Measurement Setup AMP2 3.3V VDDIO VDDIN Voltage Regulator VDDOUT AMP1 VDDCORE VDDPLL Tables below give Active Mode current consumption in typical conditions. VDDCORE at 1.2V Temperature = 25°C 43.3.3.1 SAM4S16/S8 Active Power Consumption Table 43-16. SAM4S16/S8 Active Power Consumption with VDDCORE @ 1.2V Running from Flash Memory or SRAM CoreMark Core Clock (MHz) 128-bit Flash access(1) 64-bit Flash access(1) SRAM AMP1 AMP2 AMP1 AMP2 120 24.9 28.8 18 21.
Figure 43-10.
43.3.3.2 SAM4SD32/SD16/SA16 Active Power Consumption Table 43-17. SAM4SD32/SA16/SD16 Active Power Consumption with VDDCORE @ 1.2V running from Flash Memory (IDDCORE- AMP1) or SRAM CoreMark Cache Enable (CE) Cache Disable (CD) Core Clock (MHz) 128-bit Flash access(1) 64-bit Flash access(1) 128-bit Flash access(1) 64-bit Flash access(1) SRAM 120 20.7 20.7 24.8 18.1 19.9 100 17.5 17.4 21.6 16.5 16.8 84 14.7 14.7 18.3 13.9 14.2 64 11.3 11.3 14.4 11.5 10.9 48 8.5 8.5 11.3 9.
43.3.4 Peripheral Power Consumption in Active Mode Table 43-18. Typical Power Consumption on VDDCORE(1) Peripheral Consumption VDDCORE 1.08V Consumption VDDCORE 1.2V Consumption VDDCORE 1.32V PIO Controller A (PIOA) 4.2 4.7 5.3 PIO Controller B (PIOB) 1.2 1.4 1.5 PIO Controller C (PIOC) 2.6 3.0 3.2 UART 3.8 4.2 4.6 USART 5.6 6.2 7.0 PWM 10.2 11.5 12.5 TWI 4.0 4.4 5.0 SPI 4.2 4.7 5.1 Timer Counter (TCx) 4.2 4.7 5.2 ADC 2.9 3.3 3.6 DACC 2.7 3.1 3.4 ACC 0.4 0.
43.4 Oscillator Characteristics 43.4.1 32 kHz RC Oscillator Characteristics Table 43-19. 32 kHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit RC Oscillator Frequency 20 32 44 kHz Frequency Supply Dependency -3 3 %/V Frequency Temperature Dependency Over temperature range (-40°C/ +105°C) versus 25°C -7 — 7 % Duty Duty Cycle 45 50 55 % TON Startup Time — — 100 μs — 540 860 nA Typ Max Unit 12 MHz % After startup time IDDON Temp.
43.4.3 32.768 kHz Crystal Oscillator Characteristics Table 43-21. 32.768 kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Freq Operating Frequency Normal mode with crystal Supply Ripple Voltage (on VDDIO) Rms value, 10 kHz to 10 MHz Duty Cycle 40 Rs < 50 KΩ Startup Time Rs < 100 KΩ (1) Rs < 50 KΩ Iddon Current Consumption Rs < 100 KΩ (1) Ccrystal = 12.5 pF Ccrystal = 6 pF Ccrystal = 12.5 pF Ccrystal = 6 pF Typ 50 Max Unit 32.
43.4.5 3 to 20 MHz Crystal Oscillator Characteristics Table 43-23. 3 to 20 MHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit Freq Operating Frequency Normal mode with crystal 3 16 20 MHz Supply Ripple Voltage (on VDDPLL) Rms value, 10 kHz to 10 MHz — — 30 mV 40 50 60 % Duty Cycle 3 MHz, CSHUNT = 3 pF 14.5 8 MHz, CSHUNT = 7 pF TON Startup Time 4 16 MHz, CSHUNT = 7 pF with Cm = 8 fF — — 16 MHz, CSHUNT = 7 pF with Cm = 1.
43.4.6 3 to 20 MHz Crystal Characteristics Table 43-24. Crystal Characteristics Symbol Parameter Conditions Min Typ Max 200 Fundamental @ 3 MHz Fundamental @ 8 MHz ESR Equivalent Series Resistor (Rs) Unit 100 Fundamental @ 12 MHz — — Ω 80 Fundamental @ 16 MHz 80 Fundamental @ 20 MHz 50 CM Motional Capacitance — — 8 fF CSHUNT Shunt Capacitance — — 7 pF 43.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode Table 43-25.
43.4.8 Crystal Oscillator Design Considerations Information 43.4.8.1 Choosing a Crystal When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3–20 MHz Oscillator, several parameters must be taken into account. Important parameters between crystal and SAM4S specifications are as follows: Load Capacitance Drive Level Crystal drive level ≥ Oscillator drive level. Having a crystal drive level number lower than the oscillator specification may damage the crystal.
43.5 PLLA, PLLB Characteristics Table 43-26. Supply Voltage Phase Lock Loop Characteristics Symbol Parameter Conditions Supply Voltage Range VDDPLL Allowable Voltage Ripple RMS Value 10 kHz to 10 MHz RMS Value > 10 MHz Min Typ Max Unit 1.08 1.2 1.32 V — — 20 10 mV Table 43-27. PLLA and PLLB Characteristics Symbol Parameter FIN FOUT IPLL Min Typ Max Unit Input Frequency 3 — 32 MHz Output Frequency 80 — 240 MHz Active mode @ 80 MHz @1.2V 0.94 1.
43.6 USB Transceiver Characteristics 43.6.1 Typical Connection For details on a typical connection, refer to the section on the USB Device Port. 43.6.2 Electrical Parameters Table 43-28. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit Input Levels VIL Low Level — — 0.8 V VIH High Level 2.0 — — V VDI Differential Input Sensitivity 0.2 — — V VCM Differential Input Common Mode Range 0.8 — 2.
43.6.3 Switching Characteristics Table 43-29. In Full Speed Symbol Parameter Conditions Min Typ Max Unit tFR Transition Rise Time CLOAD = 50 pF 4 — 20 ns tFE Transition Fall Time CLOAD = 50 pF 4 — 20 ns tFRFM Rise/Fall Time Matching 90 — 111.11 % Figure 43-12.
43.7 12-Bit ADC Characteristics Table 43-30. Analog Power Supply Characteristics Symbol VVDDIN Parameter Conditions Min Typ Max Units ADC Analog Supply 12-bit or 10-bit resolution 2.4 3.0 3.6 V ADC Analog Supply 10-bit resolution 2.0 — 3.6 V Max. Voltage Ripple rms value, 10 kHz to 20 MHz — — 20 mV 2 4 μA 2.4 3.5 mA 4.
43.7.1 Static Performance Characteristics In the following tables, the LSB is relative to analog scale: Single Ended (ex: ADVREF =3.0V), Gain = 1, LSB = (3.0V / 4096) = 732 μV Gain = 2, LSB = (1.5V / 4096) = 366 μV Gain = 4, LSB = (750 mV / 4096) = 183 μV Differential (ex: ADVREF =3.0V), Gain = 0.5, LSB = (6.0V / 4096) = 1465 μV Gain = 1, LSB = (3.0V / 4096) = 732 μV Gain = 2, LSB = (1.5V / 4096) = 366 μV Table 43-33. INL, DNL, 12-bit Mode, VDDIN 2.4V to 3.
Table 43-35. Static Performance Characteristics – 10-bit Mode (1) Parameter Min Typ Max Units Resolution — 10 — bit Integral Non-linearity (INL) — ±0.5 ±1 LSB — ±0.5 ±1 LSB Offset Error -10 — 10 LSB Gain Error -7 — 7 LSB Min Typ Max Units Signal to Noise Ratio - SNR 56 64 72 dB Total Harmonic Distortion - THD -84 -74 -66 dB Signal to Noise and Distortion - SINAD 55 62 71 dB Effective Number of Bits ENOB 9 10.
43.7.1.1 Track and Hold Time versus Source Output Impedance The following figure shows a simplified acquisition path. Figure 43-13.Simplified Acquisition Path ADC Input Zsource Mux. Sample & Hold 12-bit ADC Core Ron Csample During the tracking phase, the ADC needs to track the input signal during the tracking time shown below: 10-bit mode: tTRACK = 0.042 x Zsource + 160 12-bit mode: tTRACK = 0.054 x Zsource + 205 with tTRACK expressed in ns and ZSOURCE expressed in Ohms.
2. The calculated tracking time (tTRACK) is higher than 15 tCP_ADC. Set TRANSFER = 1 and TRACTIM = 0. In this case, a timer will trigger the ADC in order to set the correct sampling rate according to the track time. The maximum possible sampling frequency will be defined by tTRACK in nanoseconds, computed by the previous formula but with minus 15 × tCP_ADC and plus TRANSFER time.
43.8 12-Bit DAC Characteristics Table 43-40. Analog Power Supply Characteristics Symbol Parameter Conditions Analog Supply VVDDIN Max. Voltage Ripple rms value, 10 kHz to 20 MHz Min Typ Max Units 2.4 3.0 3.6 V — — 20 mV 3 μA 2 3 mA 4.3 5.6 mA 5 6.
Table 43-43. Dynamic Performance Characteristics Parameter Conditions Min Typ Max 2.4V < VVDDIN < 2.7V 50 62 70 2.7V < VVDDIN < 3.6V 62 70 74 2.4V < VVDDIN < 2.7V -78 -64 -60 dB Signal to Noise Ratio - SNR Total Harmonic Distortion - THD dB 2.7V < VVDDIN < 3.6V -80 -74 -72 2.4V < VVDDIN < 2.7V 50 60 70 Signal to Noise and Distortion - SINAD dB 2.7V < VVDDIN < 3.6V 62 68 73 2.4V < VVDDIN < 2.7V 8 10 12 Effective Number of Bits ENOB bits 2.7V < VVDDIN < 3.
43.9 Analog Comparator Characteristics Table 43-45. Analog Comparator Characteristics Parameter Conditions Min Typ Max Units Voltage Range The analog comparator is supplied by VDDIN 1.62 3.3 3.6 V Input Voltage Range GND + 0.2 — VDDIN - 0.
43.11 AC Characteristics 43.11.1 Master Clock Characteristics Table 43-47. Master Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.20V — 120 MHz 1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.08V — 100 MHz 43.11.
4. Pin Group 4 = PA[0–3] 5. Pin Group 5 = PB[10–11] 43.11.3 SPI Characteristics Figure 43-14.SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 43-15.SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0) SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 43-16.
Figure 43-17.SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 43.11.3.1Maximum SPI Frequency The following formulas give maximum SPI frequency in master read and write modes and in slave read and write modes. Master Write Mode The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 43.11.
43.11.3.2SPI Timings Table 43-49.
43.11.5 SSC Timings Timings are given in the following domain: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 30 pF Figure 43-18.SSC Transmitter, TK and TF as Output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 43-19.SSC Transmitter, TK as Input and TF as Output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 43-20.
Figure 43-21.SSC Transmitter, TK and TF as Input TK (CKI=1) TK (CKI=0) SSC5 SSC6 TF SSC7 TD Figure 43-22.SSC Receiver RK and RF as Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 43-23.
Figure 43-24.SSC Receiver, RK and RF as Output RK (CKI=1) RK (CKI=0) SSC12 SSC11 RD SSC13 RF Figure 43-25.SSC Receiver, RK as Output and RF as Input RK (CKI=0) RK (CKI=1) SSC12 SSC11 RF/RD Table 43-50.
Table 43-50. SSC Timings (Continued) Symbol SSC7(1) Parameter Condition TK Edge to TF/TD (TK Input, TF Input) 1.8V domain (3) 3.3V domain (4) Min Max Units 4.5(+3*tCPMCK) (1)(4) (1)(4) 16.3(+3*tCPMCK) 3.8(+3*tCPMCK) (1)(4) 13.
43.11.6 SMC Timings Timings are given in the following domain: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 50 pF. Timings are given assuming a capacitance load on data, control and address pads: In the following tables tCPMCK is MCK period. Timing extraction 43.11.6.1Read Timings Table 43-51. SMC Read Signals - NRD Controlled (READ_MODE = 1) Symbol Parameter Min VDDIO Supply Max (2) 3.3V 1.8V (3) 1.
Table 43-52. SMC Read Signals - NCS Controlled (READ_MODE = 0) (Continued) A0 - A22 Valid before NCS High (NCS rd setup + NCS rd pulse)* tCPMCK - 6.5 (NCS rd setup + NCS rd pulse)* tCPMCK - 6.3 — — ns SMC13 NRD Low before NCS High (NCS rd setup + NCS rd pulse NRD setup)* tCPMCK - 5.6 (NCS rd setup + NCS rd pulse - NRD setup)* tCPMCK- 5.4 — — ns SMC14 NCS Pulse Width NCS rd pulse NCS rd pulse length length * tCPMCK -7.7 * tCPMCK - 6.7 — — ns SMC12 43.11.6.2Write Timings Table 43-53.
Table 43-54. SMC Write NCS Controlled (WRITE_MODE = 0) Symbol Parameter Min (2) Max (3) (2) 3.3V 1.8V 1.8V 3.3V(3) Units SMC22 Data Out Valid before NCS High NCS wr pulse * tCPMCK - 6.3 NCS wr pulse * tCPMCK - 6.2 — — ns SMC23 NCS Pulse Width NCS wr pulse * tCPMCK - 7.7 NCS wr pulse * tCPMCK - 6.7 — — ns SMC24 A0 - A22 Valid before NCS Low NCS wr setup * tCPMCK - 6.5 NCS wr setup * tCPMCK - 6.
Figure 43-28.
43.11.7 USART in SPI Mode Timings Timings are given in the following domain: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF Figure 43-29.
Figure 43-31.
43.11.7.1USART SPI TImings Table 43-55. USART SPI Timings Symbol Parameter Conditions Min Max Units MCK/6 — ns 0.5 * MCK + 0.8 0.5 * MCK + 1.0 — ns 1.5 * MCK + 0.3 1.5 * MCK + 0.1 — ns 1.5 * SPCK - 1.5 1.5 * SPCK - 2.1 — ns - 7.9 - 7.2 9.9 10.7 ns 1 * SPCK - 4.1 1 * SPCK - 4.8 — ns 4.7 4 17.3 15.2 ns 2 * MCK + 0.7 2 * MCK — ns 0 0.1 — ns 4.7 4.1 17.1 15.5 ns 2 * MCK + 0.7 2 * MCK + 0.6 — ns 0.2 0.1 — ns 2,5 * MCK + 0.5 2,5 * MCK — ns 1,5 * MCK + 0.
43.11.8 Two-wire Serial Interface Characteristics Table 43-56 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer to Figure 4332. Table 43-56. Two-wire Serial Bus Requirements Symbol Parameter VIL Condition Min Max Units Input Low-voltage -0.3 0.3 VVDDIO V VIH Input High-voltage 0.7xVVDDIO VCC + 0.3 V VHYS Hysteresis of Schmitt Trigger Inputs 0.150 — V VOL Output Low-voltage 3 mA sink current - 0.4 V 20 + 0.
Figure 43-32.Two-wire Serial Bus Timing tHIGH tof tr tLOW tLOW TWCK tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO TWD tBUF 43.11.9 Embedded Flash Characteristics The maximum operating frequency given in Table 43-57 is limited by the embedded Flash access time when the processor is fetching code out of it. Table 43-57 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the embedded Flash memory.
44. SAM4S Mechanical Characteristics Figure 44-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. Table 44-1. Device and LQFP Package Maximum Weight SAM4S 800 mg Table 44-2. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e3 Table 44-3. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
Figure 44-2. 100-ball TFBGA Package Drawing Table 44-4. TFBGA Package Reference - Soldering Information (Substrate Level) Ball Land Diameter 450 μm Soldering Mask Opening 350 μm Table 44-5. Device and 100-ball TFBGA Package Maximum Weight SAM4S 141 mg Table 44-6. 100-ball TFBGA Package Characteristics Moisture Sensitivity Level 3 100-ball TFBGA Package Reference JEDEC Drawing Reference MO-275-DDAC-1 JESD97 Classification e8 This package respects the recommendations of the NEMI User Group.
Figure 44-3. 100-ball VFBGA Package Drawing Table 44-7. VFBGA Package Dimensions Symbol Package: Common Dimensions (mm) VFBGA X E 7.000 ± 0.100 Y D 7.000 ± 0.100 X eE 0.650 Y eD 0.650 Total Thickness: A 1.000 max Mold Thickness: M 0.450 ref. Substrate Thickness: S 0.210 ref. Body Size: Ball Pitch: Ball Diameter: 0.
Table 44-7. VFBGA Package Dimensions (Continued) Symbol Common Dimensions (mm) Stand Off: A1 0.160 ~ 0.260 Ball Width: b 0.270 ~ 0.370 Package Edge Tolerance: aaa 0.100 Mold Flatness: bbb 0.100 Coplanarity: ddd 0.080 Ball Offset (Package): eee 0.150 Ball Offset (Ball): fff 0.080 Ball Count: n 100 X E1 5.850 Y D1 5.850 X I 0.575 Y J 0.575 Edge Ball Center to Center: Corner Ball Center to Package Edge: Table 44-8.
Figure 44-4.
Table 44-12. 64-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
Figure 44-5. 64-lead QFN Package Drawing Table 44-16. Device and QFN Package Maximum Weight (Preliminary) SAM4S 280 mg Table 44-17. QFN Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification e3 Table 44-18. QFN Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
Figure 44-6. 64-ball WLCSP Package Mechanical Drawing Table 44-19. 64-ball WLCSP Package Dimensions (in mm) COMMON DIMENSIONS SYMBOL MIN. NOM. MAX. Total Thickness A 0.455 0.494 0.533 Stand Off A1 0.17 - 0.23 Wafer Thickness A2 0.254 +/- 0.025 D 4.424 BSC E 3.420 BSC Body Size Ball Diameter (Size) Ball/Bump Width 0.25 b 0.23 0.26 eD 0.4 eE 0.4 n 64 0.
Table 44-19. 64-ball WLCSP Package Dimensions (in mm) COMMON DIMENSIONS SYMBOL MIN. NOM. D1 2.8 BSC E1 2.8 BSC Package Edge Tolerance aaa 0.03 Coplanarity (Whole Wafer) ccc 0.075 Ball/Bump Offset (Package) ddd 0.05 Ball/Bump Offset (Ball) eee 0.015 MAX. Edge Ball Center to Center Figure 44-7. UBM Pad Installation Table 44-20. WLCSP Package Reference - Soldering Information (Substrate Level) UBM Pad (Under Bump Metallurgy) (E) 200 μm PBO2 Opening (j) 240 μm Table 44-21.
44.1 Soldering Profile Table 44-24 gives the recommended soldering profile from J-STD-020C. Table 44-24. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ± 25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 1100
45. Ordering Information Table 45-1.
Table 45-1.
Table 45-1.
SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 1104
46. Errata on SAM4S Devices 46.1 Marking All devices are marked with the Atmel logo and the ordering code. Additional marking is as follows: YYWW V XXXXXXXXX where 46.
46.2.2 Flash 46.2.2.1 Flash: Read Error after a GPNVM or Lock Bit Writing The sequence below leads to a bad read value. Fail sequence is: Read Flash @ address XXX Programming Flash: Write GPNVM or Lock Bit instructions Read Flash @ address XXX Problem Fix/Workaround A dummy read at another address needs to be included in the sequence. Sequence is: Read Flash @ address XXX Programming Flash: Write GPNVM or Lock Bit instructions Read Flash @ address YYY (dummy read) Read Flash @ address XXX 46.2.
Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during document review and approval loop. Doc. Rev. Comments 11100E Change Request Ref. Introduction Added WLCSP64 package in Section 1. “Features”, Table 1-1, “Configuration Summary”, added Figure 4-6 and 8620 Table 4-5, “64-ball WLCSP Pinout”. Updated Section 5.5 “Low-power Modes”. Added information on WFE. 9073 Added 2nd paragraph in Section 6.
Doc. Rev. Comments 11100E Change Request Ref. Mechanical Characteristics Added Figure 44-6 and associated package dimensions and soldering tables for WLCSP64 package. 8620 Soldering tables updated in Section 44. “SAM4S Mechanical Characteristics”. rfo Ordering Information New ordering codes (105 °C, reel conditioning, WLCSP package) added in Table 45-1, “Ordering Codes for SAM4S Devices”. 8620, rfo Errata Added Section 46.2.3.1 “Watchdog Not Stopped in Wait Mode” and Section 46.2.4.
Doc. Rev. Comments 11100D Change Request Ref. Introduction Deleted sleep mode for fast start-up in Section 5.7 “Fast Start-up”. 8763 Added 32 kHz trimming features in Section 1. “Features”. rfo Notes added in Section 8.1.3.1 “Flash Overview”, below Figure 8-3. Electrical Characteristics In Table 43-26, added 2 lines describing CPARASTANDBY and RPARASTANDBY parameters. 8614 In Table 43-62, Endurance line, deleted “Write/erase... @ 25°C” and 100k value.
Doc. Rev. Comments 11100C Change Request Ref. Introduction In Section 2. “Block Diagram”, USB linked to Peripheral Bridge instead of AHB Bus Matrix in Figure 2-1, Figure 8386 2-2, Figure 2-3 and Figure 2-4. Reference to the LPM bit removed in the whole datasheet. 8392 Flash rails mentioned in Section 5.1 “Power Supplies”. 8406 Section 9. “Real Time Event Management” created. 8439 WKUP[15:0] pins added on each block diagram in Section 2. “Block Diagram” and in Table 3-1, “Signal Description List”.
Doc. Rev. Comments 11100C Change Request Ref. CMCC Updated access condition from Write-only to Read-only in Section 22.5.4 “Cache Controller Status Register” and Section 22.5.10 “Cache Controller Monitor Status Register”. Index bitfield size increased from 4 to 5 bits in Section 22.5.6 “Cache Controller Maintenance Register 1”, bitfield description completed. “0xXX - 0xFC” offset replaced with “0x38 - 0xFC” in the last row in Table 22-1, “Register Mapping”.
Doc. Rev. Comments 11100C Change Request Ref. TWI NVIC and AIC changed to Interrupt Controller. Section 33.10.4.5 “PDC” removed. “This bit is only used in Master mode” removed from bitfields ENDRX, ENDTX, RXBUFF, and TXBUFE in Section 33.11.6 “TWI Status Register”. 7844 Figure 33-23 updated: SVREAD = 1 and first occurrence of RXRDY = 1. 7884 Removed “20” at the end of the 1st paragraph in Section 33.1 “Description”.
. Doc. Rev. Comments 11100B Change Request Ref. Introduction 48 pins packages (SAM4S16A and SAM4S8A devices) removed. 8100 Write Protected Registers added in “Description” on page 1. 8213 Note related to EWP and EWPL commands added in Section 8.1.3.1 “Flash Overview” on page 31. 8225 References to WFE instructions replaced by relevant bits precise descriptions. 8275 Dual bank and cache memory mentioned in “Description” on page 1 and “Configuration Summary” on page 3.
Doc. Rev. Comments 11100B Change Request Ref. RTC In Section 16.6.2 “RTC Mode Register” on page 268, formulas associated with conditions HIGHPPM = 1 and HIGHPPM = 0 have been swapped, text has been clarified. 7950 In Section 16.5.7 “RTC Accurate Clock Calibration” on page 264, paragraph describing RTC clock calibration circuitry correction updated with mention of crystal drift. 7952 SUPC References to WFE instructions deleted in Section 18.4.
Doc. Rev. Comments 11100B Change Request Ref. PMC Added a note in Section 28.2.16.7 “PMC Clock Generator Main Oscillator Register” on page 477. 7848 Max MULA/MULB value changed from 2047 to 62 in Section 28.2.16.9 “PMC Clock Generator PLLA Register” 8064 on page 480 and Section 28.2.16.10 “PMC Clock Generator PLLB Register” on page 481. Step 5 in Section 28.2.13 “Programming Sequence” on page 463: Master Clock option added in CSS field. 8170 Third paragraph added in Section 28.2.
Doc. Rev. Comments 11100A Change Request Ref. First issue.
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Signal Description . . . . . . . . . . . . . . . . . .
12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Cortex-M4 Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5 Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . 307 19.1 19.2 19.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . 307 20.
26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 597 32.1 32.2 32.3 32.4 32.5 32.6 32.7 32.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . .
37. High Speed MultiMedia Card Interface (HSMCI) . . . . . . . . . . . . . . 809 37.1 37.2 37.3 37.4 37.5 37.6 37.7 37.8 37.9 37.10 37.11 37.12 37.13 37.14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . .
42. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . 1017 42.1 42.2 42.3 42.4 42.5 42.6 42.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAM4S [DATASHEET] 11100E–ATARM–24-Jul-13 viii
Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.
