Datasheet

953
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
̶ “PWM Channel Period Update Register” on page 998
 Register group 4:
̶ “PWM Channel Dead Time Register” on page 1000
̶ “PWM Channel Dead Time Update Register” on page 1001
 Register group 5:
̶ “PWM Fault Mode Register” on page 979
̶ “PWM Fault Protection Value Register” on page 982
There are two types of Write Protection:
 SW Write Protect—can be enabled or disabled by software
 HW Write Protect—can be enabled by software but only disabled by a hardware reset of the PWM controller
Both types of Write Protect can be applied independently to a particular register group by means of the WPCMD
and WPRGx fields in the PWM_WPCR. If at least one Write Protect is active, the register group is write-protected.
The value of field WPCMD defines the action to be performed:
0: disables SW Write Protect of the register groups of which the bit WPRGx is at ‘1’
1: enables SW Write Protect of the register groups of which the bit WPRGx is at ‘1’
2: enables HW Write Protect of the register groups of which the bit WPRGx is at ‘1’
At any time, the user can determine which Write Protect is active in which register group by the fields WPSWS and
WPHWS in the “PWM Write Protection Status Register” (PWM_WPSR).
If a write access in a write-protected register is detected, then the WPVS flag in the PWM_WPSR is set and the
field WPVSRC indicates in which register the write access has been attempted, through its address offset without
the two LSBs.
The WPVS and WPVSRC fields are automatically cleared after reading the PWM_WPSR.