Datasheet

929
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
̶ Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods
̶ Synchronous Channels Supports Connection of one Peripheral DMA Controller Channel (PDC) Which
Offers Buffer Transfer Without Processor Intervention To Update Duty-Cycle Registers
 2 Independent Events Lines Intended to Synchronize ADC Conversions
̶ Programmable delay for Events Lines to delay ADC measurements
 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and PDC Transfer Requests
 8 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs
̶ 3 User Driven through PIO inputs
̶ PMC Driven when Crystal Oscillator Clock Fails
̶ ADC Controller Driven through Configurable Comparison Function
̶ Analog Comparator Controller Driven
̶ Timer/Counter Driven through Configurable Comparison Function
 Write Protected Registers
39.3 Block Diagram
Figure 39-1. Pulse Width Modulation Controller Block Diagram
APB
ADC
Co m p ar i s o n
Units
Interrupt
Controller
Interrupt Generator
event line 0
event line 1
Eve n t s
Gen er at o r
event line x
Co m p ar a t o r
Clock
Se l e c t o r
Counter
Channel 0
Dut y-Cycle
Pe r i o d
Update
APB
Interface
CLOCK
Gen er at o r
PIO
PM C
Dead-Time
Gen er at o r
Out put
Override
Fa u l t
Protection
PIO
Co m p ar a t o r
Dead-Time
Gen er at o r
Out put
Override
Fa u l t
Protection
Counter
Channel x
Dut y-Cycle
Pe r i o d
Update
Clock
Se l e c t o r
Channel x
OCx
DTOHx
DTOLx
OOOHx
PWMHx
PWMLx
OOOLx
MUX
SYN C x
PWM Controller
MCK
Channel 0
OC0
DTOH0
DTOL0
OOOH0
PWMH0
PWML0
OOOL0
PWMHx
PWMLx
PWMH0
PWML0
PWMFI0
PWMFIx