Datasheet

SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
634
32.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-
protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status
Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate
access key, WPKEY.
The protected registers are:
 “SSC Clock Mode Register” on page 637
 “SSC Receive Clock Mode Register” on page 638
 “SSC Receive Frame Mode Register” on page 640
 “SSC Transmit Clock Mode Register” on page 642
 “SSC Transmit Frame Mode Register” on page 644
 “SSC Receive Compare 0 Register” on page 650
 “SSC Receive Compare 1 Register” on page 651