Datasheet

573
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
31.5.14 Register Write Protection
To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “PIO Write Protection Mode Register” (PIO_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the “PIO Write Protection Status
Register” (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the PIO_WPSR.
The following registers can be write-protected:
 “PIO Enable Register” on page 578
 “PIO Disable Register” on page 578
 “PIO Output Enable Register” on page 580
 “PIO Output Disable Register” on page 580
 “PIO Input Filter Enable Register” on page 582
 “PIO Input Filter Disable Register” on page 582
 “PIO Multi-driver Enable Register” on page 590
 “PIO Multi-driver Disable Register” on page 590
 “PIO Pull-Up Disable Register” on page 592
 “PIO Pull-Up Enable Register” on page 592
 “PIO Peripheral ABCD Select Register 1” on page 594
 “PIO Peripheral ABCD Select Register 2” on page 595
 “PIO Output Write Enable Register” on page 601
 “PIO Output Write Disable Register” on page 601
 “PIO Pad Pull-Down Disable Register” on page 599
 “PIO Pad Pull-Down Status Register” on page 600
 “PIO Parallel Capture Mode Register” on page 612