Datasheet

223
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
12.9.1.12System Handler Control and State Register
Name: SCB_SHCSR
Access: Read /Write
Reset: 0x00 0000000
The SHCSR enables the system handlers, and indicates the pending status of the bus fault, memory management fault,
and SVC exceptions; it also indicates the active status of the system handlers.
USGFAULTENA: Usage Fault Enable
0: Disables the exception.
1: Enables the exception.
BUSFAULTENA: Bus Fault Enable
0: Disables the exception.
1: Enables the exception.
MEMFAULTENA: Memory Management Fault Enable
0: Disables the exception.
1: Enables the exception.
SVCALLPENDED: SVC Call Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
BUSFAULTPENDED: Bus Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
MEMFAULTPENDED: Memory Management Fault Exception Pending
Read:
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
USGFAULTENA BUSFAULTENA MEMFAULTENA
15 14 13 12 11 10 9 8
SVCALLPENDE
D
BUSFAULTPEN
DED
MEMFAULTPEN
DED
USGFAULTPEN
DED
SYSTICKACT PENDSVACT MONITORACT
76543210
SVCALLACT USGFAULTACT BUSFAULTACT MEMFAULTACT