Datasheet

SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
1074
path). Note that the ADC fault output connected to the PWM is not the COMPE bit. Thus the Fault Mode (FMOD)
within the PWM configuration must be FMOD = 1.
42.6.14 Register Write Protection
To prevent any single software error from corrupting ADC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “ADC Write Protection Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, the WPVS flag in the “ADC Write Protection Status
Register” (ADC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS flag is automatically reset by reading the ADC_WPSR.
The following registers can be write-protected:
 ADC Mode Register
 ADC Channel Sequence 1 Register
 ADC Channel Sequence 2 Register
 ADC Channel Enable Register
 ADC Channel Disable Register
 ADC Extended Mode Register
 ADC Compare Window Register
 ADC Channel Gain Register
 ADC Channel Offset Register
 ADC Analog Control Register