Datasheet

868
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDU-
LOCK is reset, go to Step 5. for new values.
8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update val-
ues is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2 register.
9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD).
10. The update of these registers will occur at the next PWM period of the synchronous channels when the Update
Period is elapsed. Go to Step 8. for new values.
Figure 38-11.Method 2 (UPDM=1)
Method 3: Automatic write of duty-cycle values and automatic trigger of the update
In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA Controller (PDC). The
update of the period value, the dead-time values and the update period value must be done by writing in their respective
update registers with the CPU (respectively PWM_CPRDUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK which allows to
update synchronously (at the same PWM period) the synchronous channels:
 If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the synchronous channels.
 If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period value is triggered automatically after an update period.
To configure the automatic update, the user must define a value for the Update Period by the field UPR in the “PWM
Sync Channels Update Period Register” (PWM_SCUP). The PWM controller waits UPR+1 periods of synchronous
channels before updating automatically the duty values and the update period value.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces
the number of clock cycles required for a data transfer, which improves microcontroller performance.
The PDC must write the duty-cycle values in the synchronous channels index order. For example if the channels 0, 1 and
3 are synchronous channels, the PDC must write the duty-cycle of the channel 0 first, then the duty-cycle of the channel
1, and finally the duty-cycle of the channel 3.
The status of the PDC transfer is reported in the “PWM Interrupt Status Register 2” (PWM_ISR2) by the following flags:
 WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle values and a new update
period value. It is reset to 0 when the PWM_ISR2 register is read. The user can choose to synchronize the WRDY
CCNT0
CDTYUPD
0x20
0x40
0x60
UPRCNT
0x0
0x1
0x0
0x1
0x0
0x1
CDTY
0x20
0x40
UPRUPD 0x1
0x3
WRDY
0x60
0x0
0x1
0x2
0x3
0x0
0x1
0x2
UPR
0x1
0x3